205 lines
7.6 KiB
Plaintext
205 lines
7.6 KiB
Plaintext
/*
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* Copyright (c) 2017-2018, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* ======== CC26X2R1_LAUNCHXL_NoRTOS.lds ========
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* Default Linker script for the Texas Instruments CC1352
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*/
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STACKSIZE = 1024;
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HEAPSIZE = 256; /* Size of heap buffer used by HeapMem */
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MEMORY
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{
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FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00057fa8
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/*
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* Customer Configuration Area and Bootloader Backdoor configuration in
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* flash, 40 bytes
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*/
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FLASH_CCFG (RX) : ORIGIN = 0x00057fa8, LENGTH = 0x00000058
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SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00014000
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GPRAM (RWX) : ORIGIN = 0x11000000, LENGTH = 0x00002000
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}
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REGION_ALIAS("REGION_TEXT", FLASH);
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REGION_ALIAS("REGION_BSS", SRAM);
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REGION_ALIAS("REGION_DATA", SRAM);
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REGION_ALIAS("REGION_STACK", SRAM);
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REGION_ALIAS("REGION_HEAP", SRAM);
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REGION_ALIAS("REGION_ARM_EXIDX", FLASH);
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REGION_ALIAS("REGION_ARM_EXTAB", FLASH);
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SECTIONS {
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PROVIDE (_resetVecs_base_address =
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DEFINED(_resetVecs_base_address) ? _resetVecs_base_address : 0x0);
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.resetVecs (_resetVecs_base_address) : AT (_resetVecs_base_address) {
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KEEP (*(.resetVecs))
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} > REGION_TEXT
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.ramVecs (NOLOAD) : ALIGN(1024){
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KEEP (*(.ramVecs))
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} > REGION_DATA
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/*
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* UDMACC26XX_CONFIG_BASE below must match UDMACC26XX_CONFIG_BASE defined
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* by ti/drivers/dma/UDMACC26XX.h
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* The user is allowed to change UDMACC26XX_CONFIG_BASE to move it away from
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* the default address 0x2000_1800, but remember it must be 1024 bytes aligned.
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*/
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UDMACC26XX_CONFIG_BASE = 0x20001800;
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/*
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* Define absolute addresses for the DMA channels.
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* DMA channels must always be allocated at a fixed offset from the DMA base address.
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* --------- DO NOT MODIFY -----------
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*/
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DMA_SPI0_RX_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x30);
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DMA_SPI0_TX_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x40);
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DMA_ADC_PRI_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x70);
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DMA_GPT0A_PRI_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x90);
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DMA_SPI1_RX_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x100);
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DMA_SPI1_TX_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x110);
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DMA_ADC_ALT_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x270);
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DMA_GPT0A_ALT_CONTROL_TABLE_ENTRY_ADDRESS = (UDMACC26XX_CONFIG_BASE + 0x290);
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/*
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* Allocate SPI0, SPI1, ADC, and GPTimer0 DMA descriptors at absolute addresses.
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* --------- DO NOT MODIFY -----------
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*/
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UDMACC26XX_dmaSpi0RxControlTableEntry_is_placed = 0;
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.dmaSpi0RxControlTableEntry DMA_SPI0_RX_CONTROL_TABLE_ENTRY_ADDRESS : AT (DMA_SPI0_RX_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaSpi0RxControlTableEntry)} > REGION_DATA
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UDMACC26XX_dmaSpi0TxControlTableEntry_is_placed = 0;
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.dmaSpi0TxControlTableEntry DMA_SPI0_TX_CONTROL_TABLE_ENTRY_ADDRESS : AT (DMA_SPI0_TX_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaSpi0TxControlTableEntry)} > REGION_DATA
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UDMACC26XX_dmaADCPriControlTableEntry_is_placed = 0;
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.dmaADCPriControlTableEntry DMA_ADC_PRI_CONTROL_TABLE_ENTRY_ADDRESS : AT (DMA_ADC_PRI_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaADCPriControlTableEntry)} > REGION_DATA
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UDMACC26XX_dmaGPT0APriControlTableEntry_is_placed = 0;
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.dmaGPT0APriControlTableEntry DMA_GPT0A_PRI_CONTROL_TABLE_ENTRY_ADDRESS : AT (DMA_GPT0A_PRI_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaGPT0APriControlTableEntry)} > REGION_DATA
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UDMACC26XX_dmaSpi1RxControlTableEntry_is_placed = 0;
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.dmaSpi1RxControlTableEntry DMA_SPI1_RX_CONTROL_TABLE_ENTRY_ADDRESS : AT (DMA_SPI1_RX_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaSpi1RxControlTableEntry)} > REGION_DATA
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UDMACC26XX_dmaSpi1TxControlTableEntry_is_placed = 0;
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.dmaSpi1TxControlTableEntry DMA_SPI1_TX_CONTROL_TABLE_ENTRY_ADDRESS : AT (DMA_SPI1_TX_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaSpi1TxControlTableEntry)} > REGION_DATA
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UDMACC26XX_dmaADCAltControlTableEntry_is_placed = 0;
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.dmaADCAltControlTableEntry DMA_ADC_ALT_CONTROL_TABLE_ENTRY_ADDRESS : AT (DMA_ADC_ALT_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaADCAltControlTableEntry)} > REGION_DATA
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UDMACC26XX_dmaGPT0AAltControlTableEntry_is_placed = 0;
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.dmaGPT0AAltControlTableEntry DMA_GPT0A_ALT_CONTROL_TABLE_ENTRY_ADDRESS : AT (DMA_GPT0A_ALT_CONTROL_TABLE_ENTRY_ADDRESS) {*(.dmaGPT0AAltControlTableEntry)} > REGION_DATA
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.text : {
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CREATE_OBJECT_SYMBOLS
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*(.text)
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*(.text.*)
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. = ALIGN(0x4);
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KEEP (*(.ctors))
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. = ALIGN(0x4);
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KEEP (*(.dtors))
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. = ALIGN(0x4);
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__init_array_start = .;
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KEEP (*(.init_array*))
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__init_array_end = .;
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*(.init)
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*(.fini*)
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} > REGION_TEXT AT> REGION_TEXT
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PROVIDE (__etext = .);
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PROVIDE (_etext = .);
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PROVIDE (etext = .);
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.rodata : {
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*(.rodata)
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*(.rodata.*)
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} > REGION_TEXT AT> REGION_TEXT
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.data : ALIGN(4) {
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__data_load__ = LOADADDR (.data);
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__data_start__ = .;
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*(.data)
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*(.data.*)
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. = ALIGN (4);
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__data_end__ = .;
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} > REGION_DATA AT> REGION_TEXT
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.ARM.exidx : {
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__exidx_start = .;
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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__exidx_end = .;
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} > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
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.ARM.extab : {
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
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.nvs (NOLOAD) : ALIGN(0x2000) {
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*(.nvs)
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} > REGION_TEXT
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.ccfg : {
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KEEP (*(.ccfg))
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} > FLASH_CCFG AT> FLASH_CCFG
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.bss : {
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__bss_start__ = .;
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*(.shbss)
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*(.bss)
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*(.bss.*)
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*(COMMON)
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. = ALIGN (4);
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__bss_end__ = .;
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} > REGION_BSS AT> REGION_BSS
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.heap : {
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__heap_start__ = .;
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end = __heap_start__;
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_end = end;
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__end = end;
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. = . + HEAPSIZE;
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KEEP(*(.heap))
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__heap_end__ = .;
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__HeapLimit = __heap_end__;
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} > REGION_HEAP AT> REGION_HEAP
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.stack (NOLOAD) : ALIGN(0x8) {
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_stack = .;
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__stack = .;
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KEEP(*(.stack))
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. += STACKSIZE;
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_stack_end = .;
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__stack_end = .;
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} > REGION_STACK AT> REGION_STACK
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}
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