222 lines
7.1 KiB
C
222 lines
7.1 KiB
C
/*
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* Copyright (c) 2009, University of Colombo School of Computing
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki operating system.
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*
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* @(#)$$
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*/
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/**
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* \file
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* Configuration for MICAz platform.
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*
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* \author
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* Kasun Hewage <kasun.ch@gmail.com>
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*/
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#ifndef __CONTIKI_CONF_H__
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#define __CONTIKI_CONF_H__
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#define HAVE_STDINT_H
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#include "avrdef.h"
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/*
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* MCU and clock rate.
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* MICAZ runs on 7.3728 MHz clock.
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*/
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#define MCU_MHZ 7
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#define PLATFORM PLATFORM_AVR
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/* Clock ticks per second */
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#define CLOCK_CONF_SECOND 128
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/* COM port to be used for SLIP connection */
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#define SLIP_PORT RS232_PORT_0
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/* Pre-allocated memory for loadable modules heap space (in bytes)*/
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#define MMEM_CONF_SIZE 256
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/* Use the following address for code received via the codeprop
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* facility
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*/
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#define EEPROMFS_ADDR_CODEPROP 0x8000
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#define EEPROM_NODE_ID_START 0x00
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#define TIMESYNCH_CONF_ENABLED 1
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#define CC2420_CONF_TIMESTAMPS 1
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#define WITH_NULLMAC 0
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#define CCIF
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#define CLIF
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#ifdef WITH_UIP6
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#define RIMEADDR_CONF_SIZE 8
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#define UIP_CONF_LL_802154 1
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#define UIP_CONF_LLH_LEN 0
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#define UIP_CONF_IPV6 1
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#define UIP_CONF_IPV6_QUEUE_PKT 1
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#define UIP_CONF_IPV6_CHECKS 1
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#define UIP_CONF_IPV6_REASSEMBLY 0
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#define UIP_CONF_NETIF_MAX_ADDRESSES 3
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#define UIP_CONF_ND6_MAX_PREFIXES 3
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#define UIP_CONF_ND6_MAX_NEIGHBORS 4
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#define UIP_CONF_ND6_MAX_DEFROUTERS 2
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#define UIP_CONF_IP_FORWARD 0
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#define SICSLOWPAN_CONF_COMPRESSION_IPV6 0
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#define SICSLOWPAN_CONF_COMPRESSION_HC1 1
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#define SICSLOWPAN_CONF_COMPRESSION_HC01 2
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#define SICSLOWPAN_CONF_COMPRESSION SICS_LOWPAN_CONF_COMPRESSION_HC1
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#define SICSLOWPAN_CONF_FRAG 0
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#define SICSLOWPAN_CONF_CONVENTIONAL_MAC 1
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#else
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#define UIP_CONF_IP_FORWARD 1
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#endif /* WITH_UIP6 */
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#define UIP_CONF_ICMP_DEST_UNREACH 1
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#define UIP_CONF_DHCP_LIGHT
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#define UIP_CONF_LLH_LEN 0
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#define UIP_CONF_BUFFER_SIZE 110
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#define UIP_CONF_RECEIVE_WINDOW (UIP_CONF_BUFFER_SIZE - 40)
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#define UIP_CONF_MAX_CONNECTIONS 4
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#define UIP_CONF_MAX_LISTENPORTS 8
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#define UIP_CONF_UDP_CONNS 12
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#define UIP_CONF_FWCACHE_SIZE 30
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#define UIP_CONF_BROADCAST 1
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#define UIP_ARCH_IPCHKSUM 1
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#define UIP_CONF_UDP_CHECKSUMS 1
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#define UIP_CONF_PINGADDRCONF 0
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#define UIP_CONF_LOGGING 0
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#define UIP_CONF_TCP_SPLIT 0
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/* LEDs ports. */
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#define LEDS_PxDIR DDRA // port direction register
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#define LEDS_PxOUT PORTA // port register
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#define LEDS_CONF_RED 0x04 //red led
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#define LEDS_CONF_GREEN 0x02 // green led
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#define LEDS_CONF_YELLOW 0x01 // yellow led
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/*
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* SPI bus configuration for the MicaZ.
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*/
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/* SPI input/output registers. */
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#define SPI_TXBUF SPDR
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#define SPI_RXBUF SPDR
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#define BV(bitno) _BV(bitno)
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#define SPI_WAITFOREOTx() do { while (!(SPSR & BV(SPIF))); } while (0)
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#define SPI_WAITFOREORx() do { while (!(SPSR & BV(SPIF))); } while (0)
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#define SCK 1 /* - Output: SPI Serial Clock (SCLK) - ATMEGA128 PORTB, PIN1 */
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#define MOSI 2 /* - Output: SPI Master out - slave in (MOSI) - ATMEGA128 PORTB, PIN2 */
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#define MISO 3 /* - Input: SPI Master in - slave out (MISO) - ATMEGA128 PORTB, PIN3 */
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/*
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* SPI bus - CC2420 pin configuration.
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*/
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#define FIFO_P 6 /* - Input: FIFOP from CC2420 - ATMEGA128 PORTE, PIN6 */
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#define FIFO 7 /* - Input: FIFO from CC2420 - ATMEGA128 PORTB, PIN7 */
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#define CCA 6 /* - Input: CCA from CC2420 - ATMEGA128 PORTD, PIN6 */
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#define SFD 4 /* - Input: SFD from CC2420 - ATMEGA128 PORTD, PIN4 */
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#define CSN 0 /* - Output: SPI Chip Select (CS_N) - ATMEGA128 PORTB, PIN0 */
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#define VREG_EN 5 /* - Output: VREG_EN to CC2420 - ATMEGA128 PORTA, PIN5 */
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#define RESET_N 6 /* - Output: RESET_N to CC2420 - ATMEGA128 PORTA, PIN6 */
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/* Pin status. */
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#define FIFO_IS_1 (!!(PINB & BV(FIFO)))
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#define CCA_IS_1 (!!(PIND & BV(CCA) ))
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#define RESET_IS_1 (!!(PINA & BV(RESET_N)))
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#define VREG_IS_1 (!!(PINA & BV(VREG_EN)))
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#define FIFOP_IS_1 (!!(PINE & BV(FIFO_P)))
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#define SFD_IS_1 (!!(PIND & BV(SFD)))
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/* The CC2420 reset pin. */
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#define SET_RESET_INACTIVE() ( PORTA |= BV(RESET_N) )
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#define SET_RESET_ACTIVE() ( PORTA &= ~BV(RESET_N) )
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/* CC2420 voltage regulator enable pin. */
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#define SET_VREG_ACTIVE() ( PORTA |= BV(VREG_EN) )
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#define SET_VREG_INACTIVE() ( PORTA &= ~BV(VREG_EN) )
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/* CC2420 rising edge trigger for external interrupt 6 (FIFOP).
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* Enable the external interrupt request for INT6.
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* See Atmega128 datasheet about EICRB Register
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*/
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#define FIFOP_INT_INIT() do {\
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EICRB |= 0x30; \
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CLEAR_FIFOP_INT(); \
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} while (0)
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/* FIFOP on external interrupt 6. */
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#define ENABLE_FIFOP_INT() do { EIMSK |= 0x40; } while (0)
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#define DISABLE_FIFOP_INT() do { EIMSK &= ~0x40; } while (0)
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#define CLEAR_FIFOP_INT() do { EIFR = 0x40; } while (0)
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/* Enables/disables CC2420 access to the SPI bus (not the bus).
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*
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* These guys should really be renamed but are compatible with the
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* original Chipcon naming.
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*
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* SPI_CC2420_ENABLE/SPI_CC2420_DISABLE???
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* CC2420_ENABLE_SPI/CC2420_DISABLE_SPI???
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*/
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#define SPI_ENABLE() ( PORTB &= ~BV(CSN) ) /* ENABLE CSn (active low) */
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#define SPI_DISABLE() ( PORTB |= BV(CSN) ) /* DISABLE CSn (active low) */
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typedef unsigned short clock_time_t;
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typedef unsigned short uip_stats_t;
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typedef unsigned long off_t;
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void clock_delay(unsigned int us2);
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void clock_wait(int ms10);
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void clock_set_seconds(unsigned long s);
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unsigned long clock_seconds(void);
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#endif /* __CONTIKI_CONF_H__ */
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