5261bb861d
When returning from PM1/2, the sleep timer value (used by RTIMER_NOW()) is not up-to-date until a positive edge on the 32-kHz clock has been detected after the system clock restarted. To ensure an updated value is read, wait for a positive transition on the 32-kHz clock by polling the SYS_CTRL_CLOCK_STA.SYNC_32K bit, before reading the sleep timer value. Because of this RTIMER_NOW() fixup, lpm_exit() has to be called at the very beginning of ISRs waking up the SoC. This also ensures that all clocks and timers are enabled at the correct frequency and updated before using them following wake-up. Without this fix, etimers could sometimes (randomly, depending on timings) become ultra slow (observed from 10x to 40x slower than normal) if the system exited PM1/2 very often. This issue occurred more often with PM1. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
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| .. | ||
| ana-regs.h | ||
| cc2538-rf.c | ||
| cc2538-rf.h | ||
| flash-cca.h | ||
| gpio.c | ||
| gpio.h | ||
| gptimer.h | ||
| ioc.c | ||
| ioc.h | ||
| mpu.h | ||
| nvic.c | ||
| nvic.h | ||
| random.c | ||
| rfcore-ffsm.h | ||
| rfcore-sfr.h | ||
| rfcore-xreg.h | ||
| rfcore.h | ||
| rom-util.h | ||
| scb.h | ||
| smwdthrosc.h | ||
| soc-adc.h | ||
| spi.c | ||
| ssi.h | ||
| sys-ctrl.c | ||
| sys-ctrl.h | ||
| systick.h | ||
| uart1.h | ||
| uart.c | ||
| uart.h | ||
| udma.c | ||
| udma.h | ||
| usb-regs.h | ||
| watchdog.c | ||