273 lines
8.2 KiB
C
273 lines
8.2 KiB
C
/*
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* Defines and Macros for Interrupt-Service-Routines
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* collected and partly created by
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* Martin Thomas <mthomas@rhrk.uni-kl.de>
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*
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* Copyright 2005 M. Thomas
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* No guarantees, warrantees, or promises, implied or otherwise.
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* May be used for hobby or commercial purposes provided copyright
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* notice remains intact.
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*/
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#ifndef interrupt_utils_
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#define interrupt_utils_
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/*
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The following defines are usefull for
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interrupt service routine declarations.
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*/
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/*
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RAMFUNC
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Attribute which defines a function to be located
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in memory section .fastrun and called via "long calls".
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See linker-skript and startup-code to see how the
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.fastrun-section is handled.
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The definition is not only useful for ISRs but since
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ISRs should be executed fast the macro is defined in
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this header.
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*/
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#define RAMFUNC __attribute__ ((long_call, section (".fastrun")))
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/*
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INTFUNC
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standard attribute for arm-elf-gcc which marks
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a function as ISR (for the VIC). Since gcc seems
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to produce wrong code if this attribute is used in
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thumb/thumb-interwork the attribute should only be
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used for "pure ARM-mode" binaries.
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*/
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#define INTFUNC __attribute__ ((interrupt("IRQ")))
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/*
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NACKEDFUNC
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gcc will not add any code to a function declared
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"nacked". The user has to take care to save registers
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and add the needed code for ISR functions. Some
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macros for this tasks are provided below.
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*/
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#define NACKEDFUNC __attribute__((naked))
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/******************************************************************************
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*
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* MACRO Name: ISR_STORE()
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*
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* Description:
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* This MACRO is used upon entry to an ISR with interrupt nesting.
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* Should be used together with ISR_ENABLE_NEST(). The MACRO
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* performs the following steps:
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*
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* 1 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.
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*
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*****************************************************************************/
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#define ISR_STORE() asm volatile( \
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"STMDB SP!,{R0-R12,LR}\n" )
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/******************************************************************************
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*
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* MACRO Name: ISR_RESTORE()
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*
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* Description:
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* This MACRO is used upon exit from an ISR with interrupt nesting.
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* Should be used together with ISR_DISABLE_NEST(). The MACRO
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* performs the following steps:
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*
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* 1 - Load the non-banked registers r0-r12 and lr from the IRQ stack.
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* 2 - Adjusts resume adress
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*
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*****************************************************************************/
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#define ISR_RESTORE() asm volatile( \
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"LDMIA SP!,{R0-R12,LR}\n" \
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"SUBS R15,R14,#0x0004\n" )
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/******************************************************************************
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*
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* MACRO Name: ISR_ENABLE_NEST()
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*
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* Description:
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* This MACRO is used upon entry from an ISR with interrupt nesting.
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* Should be used after ISR_STORE.
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*
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*****************************************************************************/
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#define ISR_ENABLE_NEST() asm volatile( \
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"MRS LR, SPSR \n" \
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"STMFD SP!, {LR} \n" \
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"MSR CPSR_c, #0x1f \n" \
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"STMFD SP!, {LR} " )
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/******************************************************************************
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*
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* MACRO Name: ISR_DISABLE_NEST()
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*
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* Description:
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* This MACRO is used upon entry from an ISR with interrupt nesting.
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* Should be used before ISR_RESTORE.
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*
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*****************************************************************************/
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#define ISR_DISABLE_NEST() asm volatile( \
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"LDMFD SP!, {LR} \n" \
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"MSR CPSR_c, #0x92 \n" \
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"LDMFD SP!, {LR} \n" \
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"MSR SPSR_cxsf, LR \n" )
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/*
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* The following marcos are from the file "armVIC.h" by:
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*
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* Copyright 2004, R O SoftWare
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* No guarantees, warrantees, or promises, implied or otherwise.
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* May be used for hobby or commercial purposes provided copyright
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* notice remains intact.
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*
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*/
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/******************************************************************************
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*
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* MACRO Name: ISR_ENTRY()
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*
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* Description:
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* This MACRO is used upon entry to an ISR. The current version of
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* the gcc compiler for ARM does not produce correct code for
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* interrupt routines to operate properly with THUMB code. The MACRO
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* performs the following steps:
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*
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* 1 - Adjust address at which execution should resume after servicing
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* ISR to compensate for IRQ entry
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* 2 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.
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* 3 - Get the status of the interrupted program is in SPSR.
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* 4 - Push it onto the IRQ stack as well.
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*
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*****************************************************************************/
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#define ISR_ENTRY() asm volatile(" sub lr, lr,#4\n" \
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" stmfd sp!,{r0-r12,lr}\n" \
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" mrs r1, spsr\n" \
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" stmfd sp!,{r1}")
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/******************************************************************************
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*
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* MACRO Name: ISR_EXIT()
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*
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* Description:
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* This MACRO is used to exit an ISR. The current version of the gcc
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* compiler for ARM does not produce correct code for interrupt
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* routines to operate properly with THUMB code. The MACRO performs
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* the following steps:
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*
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* 1 - Recover SPSR value from stack
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* 2 - and restore its value
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* 3 - Pop the return address & the saved general registers from
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* the IRQ stack & return
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*
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*****************************************************************************/
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#define ISR_EXIT() asm volatile(" ldmfd sp!,{r1}\n" \
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" msr spsr_c,r1\n" \
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" ldmfd sp!,{r0-r12,pc}^")
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/******************************************************************************
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*
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* Function Name: disableIRQ()
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*
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* Description:
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* This function sets the IRQ disable bit in the status register
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned disableIRQ(void);
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/******************************************************************************
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*
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* Function Name: enableIRQ()
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*
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* Description:
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* This function clears the IRQ disable bit in the status register
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned enableIRQ(void);
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/******************************************************************************
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*
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* Function Name: restoreIRQ()
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*
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* Description:
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* This function restores the IRQ disable bit in the status register
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* to the value contained within passed oldCPSR
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned restoreIRQ(unsigned oldCPSR);
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/******************************************************************************
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*
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* Function Name: disableFIQ()
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*
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* Description:
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* This function sets the FIQ disable bit in the status register
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned disableFIQ(void);
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/******************************************************************************
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*
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* Function Name: enableFIQ()
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*
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* Description:
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* This function clears the FIQ disable bit in the status register
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned enableFIQ(void);
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/******************************************************************************
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*
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* Function Name: restoreFIQ()
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*
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* Description:
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* This function restores the FIQ disable bit in the status register
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* to the value contained within passed oldCPSR
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned restoreFIQ(unsigned oldCPSR);
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#endif
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