529 lines
14 KiB
C
529 lines
14 KiB
C
/*
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* Copyright (C) 2015-2016, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "contiki.h"
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#include "i2c.h"
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#include "i2c-registers.h"
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#include "shared-isr.h"
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#define I2C_CLOCK_SPEED 25 /* kHz */
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#define I2C_FIFO_DEPTH 16
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#define I2C_STD_HCNT (I2C_CLOCK_SPEED * 4)
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#define I2C_STD_LCNT (I2C_CLOCK_SPEED * 5)
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#define I2C_FS_HCNT (I2C_CLOCK_SPEED)
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#define I2C_FS_LCNT (I2C_CLOCK_SPEED)
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#define I2C_FS_SPKLEN_LCNT_OFFSET 8
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#define I2C_FS_SPKLEN_HCNT_OFFSET 6
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#define I2C_POLLING_TIMEOUT (CLOCK_SECOND / 10)
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#define I2C_IRQ 9
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typedef enum {
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I2C_DIRECTION_READ,
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I2C_DIRECTION_WRITE
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} I2C_DIRECTION;
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struct quarkX1000_i2c_config {
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QUARKX1000_I2C_SPEED speed;
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QUARKX1000_I2C_ADDR_MODE addressing_mode;
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quarkX1000_i2c_callback cb_rx;
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quarkX1000_i2c_callback cb_tx;
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quarkX1000_i2c_callback cb_err;
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};
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struct i2c_internal_data {
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struct quarkX1000_i2c_config config;
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pci_driver_t pci;
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I2C_DIRECTION direction;
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uint8_t rx_len;
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uint8_t *rx_buffer;
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uint8_t tx_len;
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uint8_t *tx_buffer;
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uint8_t rx_tx_len;
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uint32_t hcnt;
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uint32_t lcnt;
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};
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static struct i2c_internal_data device;
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static uint32_t
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read(uint32_t offset)
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{
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uint32_t res;
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PCI_MMIO_READL(device.pci, res, offset);
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return res;
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}
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static void
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write(uint32_t offset, uint32_t val)
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{
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PCI_MMIO_WRITEL(device.pci, offset, val);
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}
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static uint32_t
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get_value(uint32_t offset, uint32_t mask, uint32_t shift)
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{
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uint32_t register_value = read(offset);
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register_value &= ~(0xFFFFFFFF - mask);
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return register_value >> shift;
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}
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static void
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set_value(uint32_t offset, uint32_t mask, uint32_t shift, uint32_t value)
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{
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uint32_t register_value = read(offset);
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register_value &= ~mask;
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register_value |= value << shift;
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write(offset, register_value);
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}
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static void
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i2c_data_read(void)
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{
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uint8_t i, rx_cnt;
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if (device.rx_len == 0)
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return;
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rx_cnt = get_value(QUARKX1000_IC_RXFLR,
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QUARKX1000_IC_RXFLR_MASK, QUARKX1000_IC_RXFLR_SHIFT);
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if (rx_cnt > device.rx_len)
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rx_cnt = device.rx_len;
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for (i = 0; i < rx_cnt; i++) {
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device.rx_buffer[i] = get_value(QUARKX1000_IC_DATA_CMD,
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QUARKX1000_IC_DATA_CMD_DAT_MASK, QUARKX1000_IC_DATA_CMD_DAT_SHIFT);
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}
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device.rx_buffer += i;
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device.rx_len -= i;
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}
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static void
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i2c_data_send(void)
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{
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uint32_t data = 0;
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uint8_t i, tx_cnt;
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if (device.rx_tx_len == 0)
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return;
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tx_cnt = I2C_FIFO_DEPTH - get_value(QUARKX1000_IC_TXFLR,
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QUARKX1000_IC_TXFLR_MASK, QUARKX1000_IC_TXFLR_SHIFT);
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if (tx_cnt > device.rx_tx_len)
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tx_cnt = device.rx_tx_len;
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for (i = 0; i < tx_cnt; i++) {
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if (device.tx_len > 0) {
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data = device.tx_buffer[i];
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if (device.tx_len == 1)
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data |= (device.rx_len > 0) ? QUARKX1000_IC_DATA_CMD_RESTART_MASK : QUARKX1000_IC_DATA_CMD_STOP_MASK;
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device.tx_len -= 1;
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} else {
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data = QUARKX1000_IC_DATA_CMD_CMD_MASK;
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if (device.rx_tx_len == 1)
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data |= QUARKX1000_IC_DATA_CMD_STOP_MASK;
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}
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write(QUARKX1000_IC_DATA_CMD, data);
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device.rx_tx_len -= 1;
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}
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device.tx_buffer += i;
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}
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static bool
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i2c_isr(void)
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{
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bool handled = false;
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if (read(QUARKX1000_IC_INTR_STAT) & QUARKX1000_IC_INTR_STAT_STOP_DET_MASK) {
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i2c_data_read();
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write(QUARKX1000_IC_INTR_MASK, 0);
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read(QUARKX1000_IC_CLR_INTR);
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if (device.direction == I2C_DIRECTION_WRITE) {
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if (device.config.cb_tx)
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device.config.cb_tx();
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} else {
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if (device.config.cb_rx)
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device.config.cb_rx();
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}
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handled = true;
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}
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if (read(QUARKX1000_IC_INTR_STAT) & QUARKX1000_IC_INTR_STAT_TX_EMPTY_MASK) {
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i2c_data_send();
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if (device.rx_tx_len <= 0) {
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set_value(QUARKX1000_IC_INTR_MASK,
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QUARKX1000_IC_INTR_STAT_TX_EMPTY_MASK, QUARKX1000_IC_INTR_STAT_TX_EMPTY_SHIFT, 0);
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set_value(QUARKX1000_IC_INTR_MASK,
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QUARKX1000_IC_INTR_STAT_STOP_DET_MASK, QUARKX1000_IC_INTR_STAT_STOP_DET_SHIFT, 1);
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}
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handled = true;
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}
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if(read(QUARKX1000_IC_INTR_STAT) & QUARKX1000_IC_INTR_STAT_RX_FULL_MASK) {
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i2c_data_read();
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handled = true;
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}
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if (read(QUARKX1000_IC_INTR_STAT) & (QUARKX1000_IC_INTR_STAT_TX_ABRT_MASK
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| QUARKX1000_IC_INTR_STAT_TX_OVER_MASK | QUARKX1000_IC_INTR_STAT_RX_OVER_MASK
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| QUARKX1000_IC_INTR_STAT_RX_UNDER_MASK)) {
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write(QUARKX1000_IC_INTR_MASK, 0);
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read(QUARKX1000_IC_CLR_INTR);
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if (device.config.cb_err)
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device.config.cb_err();
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handled = true;
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}
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return handled;
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}
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void
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quarkX1000_i2c_configure(QUARKX1000_I2C_SPEED speed,
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QUARKX1000_I2C_ADDR_MODE addressing_mode)
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{
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uint32_t hcnt, lcnt;
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uint8_t ic_fs_spklen;
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device.config.speed = speed;
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device.config.addressing_mode = addressing_mode;
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if (device.config.speed == QUARKX1000_I2C_SPEED_STANDARD) {
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lcnt = I2C_STD_LCNT;
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hcnt = I2C_STD_HCNT;
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} else {
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lcnt = I2C_FS_LCNT;
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hcnt = I2C_FS_HCNT;
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}
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ic_fs_spklen = get_value(QUARKX1000_IC_FS_SPKLEN,
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QUARKX1000_IC_FS_SPKLEN_MASK, QUARKX1000_IC_FS_SPKLEN_SHIFT);
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/* We adjust the Low Count and High Count based on the Spike Suppression Limit */
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device.lcnt = (lcnt < (ic_fs_spklen + I2C_FS_SPKLEN_LCNT_OFFSET)) ? ic_fs_spklen + I2C_FS_SPKLEN_LCNT_OFFSET : lcnt;
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device.hcnt = (hcnt < (ic_fs_spklen + I2C_FS_SPKLEN_HCNT_OFFSET)) ? ic_fs_spklen + I2C_FS_SPKLEN_HCNT_OFFSET : hcnt;
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/* Clear interrupts. */
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read(QUARKX1000_IC_CLR_INTR);
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}
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void
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quarkX1000_i2c_set_callbacks(quarkX1000_i2c_callback rx,
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quarkX1000_i2c_callback tx,
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quarkX1000_i2c_callback err)
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{
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device.config.cb_rx = rx;
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device.config.cb_tx = tx;
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device.config.cb_err = err;
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}
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static int
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i2c_setup(void)
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{
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/* Clear all values */
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write(QUARKX1000_IC_CON, 0);
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/* Clear interrupts */
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read(QUARKX1000_IC_CLR_INTR);
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/* Quark X1000 SoC I2C only supports master mode. */
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set_value(QUARKX1000_IC_CON,
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QUARKX1000_IC_CON_MASTER_MODE_MASK, QUARKX1000_IC_CON_MASTER_MODE_SHIFT, 1);
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/* Set restart enable */
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set_value(QUARKX1000_IC_CON,
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QUARKX1000_IC_CON_RESTART_EN_MASK, QUARKX1000_IC_CON_RESTART_EN_SHIFT, 1);
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/* Set addressing mode */
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if (device.config.addressing_mode == QUARKX1000_I2C_ADDR_MODE_10BIT) {
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set_value(QUARKX1000_IC_CON,
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QUARKX1000_IC_CON_10BITADDR_MASTER_MASK, QUARKX1000_IC_CON_10BITADDR_MASTER_SHIFT, 1);
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}
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if (device.config.speed == QUARKX1000_I2C_SPEED_STANDARD) {
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set_value(QUARKX1000_IC_SS_SCL_LCNT,
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QUARKX1000_IC_SS_SCL_LCNT_MASK, QUARKX1000_IC_SS_SCL_LCNT_SHIFT, device.lcnt);
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set_value(QUARKX1000_IC_SS_SCL_HCNT,
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QUARKX1000_IC_SS_SCL_HCNT_MASK, QUARKX1000_IC_SS_SCL_HCNT_SHIFT, device.hcnt);
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set_value(QUARKX1000_IC_CON,
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QUARKX1000_IC_CON_SPEED_MASK, QUARKX1000_IC_CON_SPEED_SHIFT, 0x1);
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} else {
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set_value(QUARKX1000_IC_FS_SCL_LCNT,
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QUARKX1000_IC_FS_SCL_LCNT_MASK, QUARKX1000_IC_FS_SCL_LCNT_SHIFT, device.lcnt);
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set_value(QUARKX1000_IC_FS_SCL_HCNT,
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QUARKX1000_IC_FS_SCL_HCNT_MASK, QUARKX1000_IC_FS_SCL_HCNT_SHIFT, device.hcnt);
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set_value(QUARKX1000_IC_CON,
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QUARKX1000_IC_CON_SPEED_MASK, QUARKX1000_IC_CON_SPEED_SHIFT, 0x2);
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}
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return 0;
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}
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static void
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i2c_operation_setup(uint8_t *write_buf, uint8_t write_len,
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uint8_t *read_buf, uint8_t read_len, uint16_t addr)
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{
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device.rx_len = read_len;
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device.rx_buffer = read_buf;
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device.tx_len = write_len;
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device.tx_buffer = write_buf;
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device.rx_tx_len = device.rx_len + device.tx_len;
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/* Disable controller */
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set_value(QUARKX1000_IC_ENABLE,
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QUARKX1000_IC_ENABLE_MASK, QUARKX1000_IC_ENABLE_SHIFT, 0);
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i2c_setup();
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/* Disable interrupts */
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write(QUARKX1000_IC_INTR_MASK, 0);
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/* Clear interrupts */
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read(QUARKX1000_IC_CLR_INTR);
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/* Set address of target slave */
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set_value(QUARKX1000_IC_TAR,
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QUARKX1000_IC_TAR_MASK, QUARKX1000_IC_TAR_SHIFT, addr);
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}
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/* This is an interrupt based operation */
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static int
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i2c_operation(uint8_t *write_buf, uint8_t write_len,
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uint8_t *read_buf, uint8_t read_len, uint16_t addr)
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{
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if (read(QUARKX1000_IC_STATUS) & QUARKX1000_IC_STATUS_ACTIVITY_MASK)
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return -1;
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i2c_operation_setup(write_buf, write_len, read_buf, read_len, addr);
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/* Enable master TX and RX interrupts */
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set_value(QUARKX1000_IC_INTR_MASK,
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QUARKX1000_IC_INTR_STAT_TX_OVER_MASK, QUARKX1000_IC_INTR_STAT_TX_OVER_SHIFT, 1);
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set_value(QUARKX1000_IC_INTR_MASK,
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QUARKX1000_IC_INTR_STAT_TX_EMPTY_MASK, QUARKX1000_IC_INTR_STAT_TX_EMPTY_SHIFT, 1);
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set_value(QUARKX1000_IC_INTR_MASK,
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QUARKX1000_IC_INTR_STAT_TX_ABRT_MASK, QUARKX1000_IC_INTR_STAT_TX_ABRT_SHIFT, 1);
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set_value(QUARKX1000_IC_INTR_MASK,
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QUARKX1000_IC_INTR_STAT_RX_UNDER_MASK, QUARKX1000_IC_INTR_STAT_RX_UNDER_SHIFT, 1);
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set_value(QUARKX1000_IC_INTR_MASK,
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QUARKX1000_IC_INTR_STAT_RX_OVER_MASK, QUARKX1000_IC_INTR_STAT_RX_OVER_SHIFT, 1);
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set_value(QUARKX1000_IC_INTR_MASK,
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QUARKX1000_IC_INTR_STAT_RX_FULL_MASK, QUARKX1000_IC_INTR_STAT_RX_FULL_SHIFT, 1);
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set_value(QUARKX1000_IC_INTR_MASK,
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QUARKX1000_IC_INTR_STAT_STOP_DET_MASK, QUARKX1000_IC_INTR_STAT_STOP_DET_SHIFT, 1);
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/* Enable controller */
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set_value(QUARKX1000_IC_ENABLE,
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QUARKX1000_IC_ENABLE_MASK, QUARKX1000_IC_ENABLE_SHIFT, 1);
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return 0;
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}
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/* This is an interrupt based write */
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int
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quarkX1000_i2c_write(uint8_t *buf, uint8_t len, uint16_t addr)
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{
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device.direction = I2C_DIRECTION_WRITE;
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return i2c_operation(buf, len, 0, 0, addr);
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}
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/* This is an interrupt based read */
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int
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quarkX1000_i2c_read(uint8_t *buf, uint8_t len, uint16_t addr)
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{
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device.direction = I2C_DIRECTION_READ;
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return i2c_operation(0, 0, buf, len, addr);
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}
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static int
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i2c_polling_operation(uint8_t *write_buf, uint8_t write_len,
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uint8_t *read_buf, uint8_t read_len, uint16_t addr)
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{
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uint32_t start_time, intr_mask_stat;
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if (!(read(QUARKX1000_IC_CON) & QUARKX1000_IC_CON_MASTER_MODE_MASK))
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return -1;
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/* Wait i2c idle */
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start_time = clock_seconds();
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while (read(QUARKX1000_IC_STATUS) & QUARKX1000_IC_STATUS_ACTIVITY_MASK) {
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if ((clock_seconds() - start_time) > I2C_POLLING_TIMEOUT) {
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return -1;
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}
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}
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/* Get interrupt mask to restore in the end of polling operation */
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intr_mask_stat = read(QUARKX1000_IC_INTR_MASK);
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i2c_operation_setup(write_buf, write_len, read_buf, read_len, addr);
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/* Enable controller */
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set_value(QUARKX1000_IC_ENABLE,
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QUARKX1000_IC_ENABLE_MASK, QUARKX1000_IC_ENABLE_SHIFT, 1);
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/* Transmit */
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if (device.tx_len != 0) {
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while (device.tx_len > 0) {
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start_time = clock_seconds();
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while (!(read(QUARKX1000_IC_STATUS) & QUARKX1000_IC_STATUS_TFNF_MASK)) {
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if ((clock_seconds() - start_time) > I2C_POLLING_TIMEOUT) {
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set_value(QUARKX1000_IC_ENABLE,
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QUARKX1000_IC_ENABLE_MASK, QUARKX1000_IC_ENABLE_SHIFT, 0);
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return -1;
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}
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}
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i2c_data_send();
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}
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start_time = clock_seconds();
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while (!(read(QUARKX1000_IC_STATUS) & QUARKX1000_IC_STATUS_TFE_MASK)) {
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if ((clock_seconds() - start_time) > I2C_POLLING_TIMEOUT) {
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set_value(QUARKX1000_IC_ENABLE,
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QUARKX1000_IC_ENABLE_MASK, QUARKX1000_IC_ENABLE_SHIFT, 0);
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return -1;
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}
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}
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}
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i2c_data_send();
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/* Receive */
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if (device.rx_len != 0) {
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while (device.rx_len > 0) {
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start_time = clock_seconds();
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while (!(read(QUARKX1000_IC_STATUS) & QUARKX1000_IC_STATUS_RFNE_MASK)) {
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if ((clock_seconds() - start_time) > I2C_POLLING_TIMEOUT) {
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set_value(QUARKX1000_IC_ENABLE,
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QUARKX1000_IC_ENABLE_MASK, QUARKX1000_IC_ENABLE_SHIFT, 0);
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return -1;
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}
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}
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i2c_data_read();
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}
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}
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/* Stop Det */
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start_time = clock_seconds();
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while (!(read(QUARKX1000_IC_RAW_INTR_STAT) & QUARKX1000_IC_INTR_STAT_STOP_DET_MASK)) {
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if ((clock_seconds() - start_time) > I2C_POLLING_TIMEOUT) {
|
|
set_value(QUARKX1000_IC_ENABLE,
|
|
QUARKX1000_IC_ENABLE_MASK, QUARKX1000_IC_ENABLE_SHIFT, 0);
|
|
return -1;
|
|
}
|
|
}
|
|
read(QUARKX1000_IC_CLR_STOP_DET);
|
|
|
|
/* Wait i2c idle */
|
|
start_time = clock_seconds();
|
|
while (read(QUARKX1000_IC_STATUS) & QUARKX1000_IC_STATUS_ACTIVITY_MASK) {
|
|
if ((clock_seconds() - start_time) > I2C_POLLING_TIMEOUT) {
|
|
set_value(QUARKX1000_IC_ENABLE,
|
|
QUARKX1000_IC_ENABLE_MASK, QUARKX1000_IC_ENABLE_SHIFT, 0);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
/* Disable controller */
|
|
set_value(QUARKX1000_IC_ENABLE,
|
|
QUARKX1000_IC_ENABLE_MASK, QUARKX1000_IC_ENABLE_SHIFT, 0);
|
|
|
|
/* Restore interrupt mask */
|
|
write(QUARKX1000_IC_INTR_MASK, intr_mask_stat);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
quarkX1000_i2c_polling_write(uint8_t *buf, uint8_t len, uint16_t addr)
|
|
{
|
|
device.direction = I2C_DIRECTION_WRITE;
|
|
return i2c_polling_operation(buf, len, 0, 0, addr);
|
|
}
|
|
|
|
int
|
|
quarkX1000_i2c_polling_read(uint8_t *buf, uint8_t len, uint16_t addr)
|
|
{
|
|
device.direction = I2C_DIRECTION_READ;
|
|
return i2c_polling_operation(0, 0, buf, len ,addr);
|
|
}
|
|
|
|
int
|
|
quarkX1000_i2c_is_available(void)
|
|
{
|
|
return device.pci.mmio ? 1 : 0;
|
|
}
|
|
|
|
DEFINE_SHARED_IRQ(I2C_IRQ, IRQAGENT3, INTC, PIRQC, i2c_isr);
|
|
|
|
int
|
|
quarkX1000_i2c_init(void)
|
|
{
|
|
pci_config_addr_t pci_addr;
|
|
|
|
pci_addr.raw = 0;
|
|
pci_addr.bus = 0;
|
|
pci_addr.dev = 21;
|
|
pci_addr.func = 2;
|
|
pci_addr.reg_off = PCI_CONFIG_REG_BAR0;
|
|
|
|
pci_command_enable(pci_addr, PCI_CMD_1_MEM_SPACE_EN);
|
|
|
|
pci_init(&device.pci, pci_addr, 0);
|
|
|
|
return 0;
|
|
}
|