b3ea790449
Add functions providing the last reset cause, one as an integer (ID), and one as a string. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
343 lines
15 KiB
C
343 lines
15 KiB
C
/*
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* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538
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* @{
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*
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* \defgroup cc2538-sys-ctrl cc2538 System Control (SysCtrl)
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*
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* Driver for the cc2538 System Control Module
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* @{
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*
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* \file
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* Header file for the cc2538 System Control driver
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*/
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#ifndef SYS_CTRL_H_
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#define SYS_CTRL_H_
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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/** \name SysCtrl Constants, used by the SYS_DIV and IO_DIV bits of the
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* SYS_CTRL_CLOCK_CTRL register
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* @{
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*/
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#define SYS_CTRL_32MHZ 32000000
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#define SYS_CTRL_16MHZ 16000000
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#define SYS_CTRL_8MHZ 8000000
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#define SYS_CTRL_4MHZ 4000000
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#define SYS_CTRL_2MHZ 2000000
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#define SYS_CTRL_1MHZ 1000000
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#define SYS_CTRL_500KHZ 500000
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#define SYS_CTRL_250KHZ 250000
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name Definitions of Sys Ctrl registers
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* @{
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*/
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#define SYS_CTRL_CLOCK_CTRL 0x400D2000 /**< Clock control register */
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#define SYS_CTRL_CLOCK_STA 0x400D2004 /**< Clock status register */
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#define SYS_CTRL_RCGCGPT 0x400D2008 /**< GPT[3:0] clocks - active mode */
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#define SYS_CTRL_SCGCGPT 0x400D200C /**< GPT[3:0] clocks - sleep mode */
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#define SYS_CTRL_DCGCGPT 0x400D2010 /**< GPT[3:0] clocks - PM0 */
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#define SYS_CTRL_SRGPT 0x400D2014 /**< GPT[3:0] reset control */
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#define SYS_CTRL_RCGCSSI 0x400D2018 /**< SSI[1:0] clocks - active mode */
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#define SYS_CTRL_SCGCSSI 0x400D201C /**< SSI[1:0] clocks - sleep mode */
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#define SYS_CTRL_DCGCSSI 0x400D2020 /**< SSI[1:0] clocks - PM0 mode */
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#define SYS_CTRL_SRSSI 0x400D2024 /**< SSI[1:0] reset control */
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#define SYS_CTRL_RCGCUART 0x400D2028 /**< UART[1:0] clocks - active mode */
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#define SYS_CTRL_SCGCUART 0x400D202C /**< UART[1:0] clocks - sleep mode */
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#define SYS_CTRL_DCGCUART 0x400D2030 /**< UART[1:0] clocks - PM0 */
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#define SYS_CTRL_SRUART 0x400D2034 /**< UART[1:0] reset control */
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#define SYS_CTRL_RCGCI2C 0x400D2038 /**< I2C clocks - active mode */
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#define SYS_CTRL_SCGCI2C 0x400D203C /**< I2C clocks - sleep mode */
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#define SYS_CTRL_DCGCI2C 0x400D2040 /**< I2C clocks - PM0 */
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#define SYS_CTRL_SRI2C 0x400D2044 /**< I2C clocks - reset control */
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#define SYS_CTRL_RCGCSEC 0x400D2048 /**< Sec Mod clocks - active mode */
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#define SYS_CTRL_SCGCSEC 0x400D204C /**< Sec Mod clocks - sleep mode */
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#define SYS_CTRL_DCGCSEC 0x400D2050 /**< Sec Mod clocks - PM0 */
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#define SYS_CTRL_SRSEC 0x400D2054 /**< Sec Mod reset control */
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#define SYS_CTRL_PMCTL 0x400D2058 /**< Power Mode Control */
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#define SYS_CTRL_SRCRC 0x400D205C /**< CRC on state retention */
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#define SYS_CTRL_PWRDBG 0x400D2074 /**< Power debug register */
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#define SYS_CTRL_CLD 0x400D2080 /**< clock loss detection feature */
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#define SYS_CTRL_IWE 0x400D2094 /**< interrupt wake-up. */
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#define SYS_CTRL_I_MAP 0x400D2098 /**< Interrupt map select */
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#define SYS_CTRL_RCGCRFC 0x400D20A8 /**< RF Core clocks - active mode */
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#define SYS_CTRL_SCGCRFC 0x400D20AC /**< RF Core clocks - Sleep mode */
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#define SYS_CTRL_DCGCRFC 0x400D20B0 /**< RF Core clocks - PM0 */
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#define SYS_CTRL_EMUOVR 0x400D20B4 /**< Emulator override */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_CLOCK_CTRL register bit masks
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* @{
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*/
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#define SYS_CTRL_CLOCK_CTRL_OSC32K_CALDIS 0x02000000
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#define SYS_CTRL_CLOCK_CTRL_OSC32K 0x01000000
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#define SYS_CTRL_CLOCK_CTRL_AMP_DET 0x00200000
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#define SYS_CTRL_CLOCK_CTRL_OSC_PD 0x00020000
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#define SYS_CTRL_CLOCK_CTRL_OSC 0x00010000
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#define SYS_CTRL_CLOCK_CTRL_IO_DIV 0x00000700
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#define SYS_CTRL_CLOCK_CTRL_SYS_DIV 0x00000007
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_CLOCK_STA register bit masks
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* @{
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*/
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#define SYS_CTRL_CLOCK_STA_SYNC_32K 0x04000000
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#define SYS_CTRL_CLOCK_STA_OSC32K_CALDIS 0x02000000
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#define SYS_CTRL_CLOCK_STA_OSC32K 0x01000000
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#define SYS_CTRL_CLOCK_STA_RST 0x00C00000
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#define SYS_CTRL_CLOCK_STA_RST_S 22
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#define SYS_CTRL_CLOCK_STA_RST_POR 0
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#define SYS_CTRL_CLOCK_STA_RST_EXT 1
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#define SYS_CTRL_CLOCK_STA_RST_WDT 2
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#define SYS_CTRL_CLOCK_STA_RST_CLD_SW 3
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#define SYS_CTRL_CLOCK_STA_SOURCE_CHANGE 0x00100000
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#define SYS_CTRL_CLOCK_STA_XOSC_STB 0x00080000
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#define SYS_CTRL_CLOCK_STA_HSOSC_STB 0x00040000
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#define SYS_CTRL_CLOCK_STA_OSC_PD 0x00020000
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#define SYS_CTRL_CLOCK_STA_OSC 0x00010000
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#define SYS_CTRL_CLOCK_STA_IO_DIV 0x00000700
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#define SYS_CTRL_CLOCK_STA_RTCLK_FREQ 0x00000018
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#define SYS_CTRL_CLOCK_STA_SYS_DIV 0x00000007
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_RCGCGPT register bit masks
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* @{
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*/
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#define SYS_CTRL_RCGCGPT_GPT3 0x00000008 /**< GPT3 clock enable, CPU running */
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#define SYS_CTRL_RCGCGPT_GPT2 0x00000004 /**< GPT2 clock enable, CPU running */
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#define SYS_CTRL_RCGCGPT_GPT1 0x00000002 /**< GPT1 clock enable, CPU running */
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#define SYS_CTRL_RCGCGPT_GPT0 0x00000001 /**< GPT0 clock enable, CPU running */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_SCGCGPT register bit masks
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* @{
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*/
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#define SYS_CTRL_SCGCGPT_GPT3 0x00000008 /**< GPT3 clock enable, CPU IDLE */
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#define SYS_CTRL_SCGCGPT_GPT2 0x00000004 /**< GPT2 clock enable, CPU IDLE */
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#define SYS_CTRL_SCGCGPT_GPT1 0x00000002 /**< GPT1 clock enable, CPU IDLE */
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#define SYS_CTRL_SCGCGPT_GPT0 0x00000001 /**< GPT0 clock enable, CPU IDLE */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_DCGCGPT register bit masks
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* @{
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*/
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#define SYS_CTRL_DCGCGPT_GPT3 0x00000008 /**< GPT3 clock enable, PM0 */
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#define SYS_CTRL_DCGCGPT_GPT2 0x00000004 /**< GPT2 clock enable, PM0 */
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#define SYS_CTRL_DCGCGPT_GPT1 0x00000002 /**< GPT1 clock enable, PM0 */
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#define SYS_CTRL_DCGCGPT_GPT0 0x00000001 /**< GPT0 clock enable, PM0 */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_SRGPT register bits
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* @{
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*/
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#define SYS_CTRL_SRGPT_GPT3 0x00000008 /**< GPT3 is reset */
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#define SYS_CTRL_SRGPT_GPT2 0x00000004 /**< GPT2 is reset */
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#define SYS_CTRL_SRGPT_GPT1 0x00000002 /**< GPT1 is reset */
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#define SYS_CTRL_SRGPT_GPT0 0x00000001 /**< GPT0 is reset */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_RCGCSEC register bit masks
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* @{
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*/
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#define SYS_CTRL_RCGCSEC_AES 0x00000002 /**< AES clock enable, CPU running */
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#define SYS_CTRL_RCGCSEC_PKA 0x00000001 /**< PKA clock enable, CPU running */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_SCGCSEC register bit masks
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* @{
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*/
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#define SYS_CTRL_SCGCSEC_AES 0x00000002 /**< AES clock enable, CPU IDLE */
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#define SYS_CTRL_SCGCSEC_PKA 0x00000001 /**< PKA clock enable, CPU IDLE */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_DCGCSEC register bit masks
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* @{
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*/
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#define SYS_CTRL_DCGCSEC_AES 0x00000002 /**< AES clock enable, PM0 */
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#define SYS_CTRL_DCGCSEC_PKA 0x00000001 /**< PKA clock enable, PM0 */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_SRSEC register bits
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* @{
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*/
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#define SYS_CTRL_SRSEC_AES 0x00000002 /**< AES is reset */
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#define SYS_CTRL_SRSEC_PKA 0x00000001 /**< PKA is reset */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_PWRDBG register bits
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* @{
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*/
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#define SYS_CTRL_PWRDBG_FORCE_WARM_RESET 0x00000008
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name Possible values for the SYS_CTRL_CLOCK_CTRL_SYS_DIV bits
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* @{
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*/
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#define SYS_CTRL_CLOCK_CTRL_SYS_DIV_32MHZ 0x00000000
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#define SYS_CTRL_CLOCK_CTRL_SYS_DIV_16MHZ 0x00000001
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#define SYS_CTRL_CLOCK_CTRL_SYS_DIV_8MHZ 0x00000002
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#define SYS_CTRL_CLOCK_CTRL_SYS_DIV_4MHZ 0x00000003
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#define SYS_CTRL_CLOCK_CTRL_SYS_DIV_2MHZ 0x00000004
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#define SYS_CTRL_CLOCK_CTRL_SYS_DIV_1MHZ 0x00000005
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#define SYS_CTRL_CLOCK_CTRL_SYS_DIV_500KHZ 0x00000006
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#define SYS_CTRL_CLOCK_CTRL_SYS_DIV_250KHZ 0x00000007
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name Possible values for the SYS_CTRL_CLOCK_CTRL_IO_DIV bits
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* @{
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*/
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#define SYS_CTRL_CLOCK_CTRL_IO_DIV_32MHZ 0x00000000
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#define SYS_CTRL_CLOCK_CTRL_IO_DIV_16MHZ 0x00000100
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#define SYS_CTRL_CLOCK_CTRL_IO_DIV_8MHZ 0x00000200
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#define SYS_CTRL_CLOCK_CTRL_IO_DIV_4MHZ 0x00000300
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#define SYS_CTRL_CLOCK_CTRL_IO_DIV_2MHZ 0x00000400
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#define SYS_CTRL_CLOCK_CTRL_IO_DIV_1MHZ 0x00000500
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#define SYS_CTRL_CLOCK_CTRL_IO_DIV_500KHZ 0x00000600
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#define SYS_CTRL_CLOCK_CTRL_IO_DIV_250KHZ 0x00000700
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_RCGCUART Register Bit-Masks
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* @{
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*/
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#define SYS_CTRL_RCGCUART_UART1 0x00000002 /**< UART1 Clock, CPU running */
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#define SYS_CTRL_RCGCUART_UART0 0x00000001 /**< UART0 Clock, CPU running */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_SCGCUART Register Bit-Masks
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* @{
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*/
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#define SYS_CTRL_SCGCUART_UART1 0x00000002 /**< UART1 Clock, CPU IDLE */
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#define SYS_CTRL_SCGCUART_UART0 0x00000001 /**< UART0 Clock, CPU IDLE */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_RCGCUART Register Bit-Masks
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* @{
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*/
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#define SYS_CTRL_DCGCUART_UART1 0x00000002 /**< UART1 Clock, PM0 */
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#define SYS_CTRL_DCGCUART_UART0 0x00000001 /**< UART0 Clock, PM0 */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_SRUART register bits
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* @{
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*/
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#define SYS_CTRL_SRUART_UART1 0x00000002 /**< UART1 module is reset */
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#define SYS_CTRL_SRUART_UART0 0x00000001 /**< UART0 module is reset */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SYS_CTRL_PMCTL register values
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* @{
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*/
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#define SYS_CTRL_PMCTL_PM3 0x00000003 /**< PM3 */
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#define SYS_CTRL_PMCTL_PM2 0x00000002 /**< PM2 */
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#define SYS_CTRL_PMCTL_PM1 0x00000001 /**< PM1 */
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#define SYS_CTRL_PMCTL_PM0 0x00000000 /**< PM0 */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SysCtrl 32-kHz oscillator selection
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*
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* Prefer the crystal oscillator for time accuracy, and the RC oscillator for
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* cost and power consumption
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* @{
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*/
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/* Defaults to RC oscillator unless the configuration tells us otherwise */
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#ifdef SYS_CTRL_CONF_OSC32K_USE_XTAL
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#define SYS_CTRL_OSC32K_USE_XTAL SYS_CTRL_CONF_OSC32K_USE_XTAL
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#else
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#define SYS_CTRL_OSC32K_USE_XTAL 0
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#endif
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name System clock divisor selection
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* @{
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*/
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#ifdef SYS_CTRL_CONF_SYS_DIV
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#if SYS_CTRL_CONF_SYS_DIV & ~SYS_CTRL_CLOCK_CTRL_SYS_DIV
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#error Invalid system clock divisor
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#endif
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#define SYS_CTRL_SYS_DIV SYS_CTRL_CONF_SYS_DIV
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#else
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#define SYS_CTRL_SYS_DIV SYS_CTRL_CLOCK_CTRL_SYS_DIV_16MHZ
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#endif
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#ifdef SYS_CTRL_CONF_IO_DIV
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#if SYS_CTRL_CONF_IO_DIV & ~SYS_CTRL_CLOCK_CTRL_IO_DIV
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#error Invalid I/O clock divisor
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#endif
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#define SYS_CTRL_IO_DIV SYS_CTRL_CONF_IO_DIV
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#else
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#define SYS_CTRL_IO_DIV SYS_CTRL_CLOCK_CTRL_IO_DIV_16MHZ
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#endif
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/* Returns actual system clock in Hz */
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#define SYS_CTRL_SYS_CLOCK (SYS_CTRL_32MHZ >> SYS_CTRL_SYS_DIV)
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/* Returns actual I/O clock in Hz */
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#define SYS_CTRL_IO_CLOCK (SYS_CTRL_32MHZ >> (SYS_CTRL_IO_DIV >> 8))
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SysCtrl functions
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* @{
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*/
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/** \brief Gets the cause of the last reset
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* \return A \c SYS_CTRL_CLOCK_STA_RST_x reset cause
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*/
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int sys_ctrl_get_reset_cause(void);
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/** \brief Gets a string describing the cause of the last reset
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* \return Last reset cause as a string
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*/
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const char *sys_ctrl_get_reset_cause_str(void);
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/** \brief Initialises the System Control Driver. The main purpose of this
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* function is to power up and select clocks and oscillators
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* \note This function depends on ioc_init() having been called beforehand. */
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void sys_ctrl_init();
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/** \brief Generates a warm reset through the SYS_CTRL_PWRDBG register */
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void sys_ctrl_reset();
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/** \brief Returns the actual system clock in Hz */
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uint32_t sys_ctrl_get_sys_clock();
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/** \brief Returns the actual io clock in Hz */
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uint32_t sys_ctrl_get_io_clock();
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/** @} */
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#endif /* SYS_CTRL_H_ */
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/**
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* @}
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* @}
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*/
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