407 lines
20 KiB
C
407 lines
20 KiB
C
/*
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* Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*---------------------------------------------------------------------------*/
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/*
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* Parameter summary
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* Address: 0
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* Address0: 0xAA
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* Address1: 0xBB
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* Frequency: 915.00000 MHz
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* Data Format: Serial mode disable
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* Deviation: 25.000 kHz
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* pktLen: 30
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* 802.15.4g Mode: 0
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* Select bit order to transmit PSDU octets:: 1
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* Packet Length Config: Variable
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* Max Packet Length: 255
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* Packet Length: 20
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* Packet Data: 255
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* RX Filter BW: 98.0 kHz
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* Symbol Rate: 50.00000 kBaud
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* Sync Word Length: 24 Bits
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* For Default PA:
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* Enable high output power PA: false
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* TX Power: 13.5 dBm (requires define CCFG_FORCE_VDDR_HH = 1 in ccfg.c,
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* see CC13xx/CC26xx Technical Reference Manual)
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* For High PA:
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* Enable high output power PA: true
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* TX Power: 20 dBm (requires define CCFG_FORCE_VDDR_HH = 0 in ccfg.c,
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* see CC13xx/CC26xx Technical Reference Manual)
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* Whitening: Dynamically IEEE 802.15.4g compatible whitener and 16/32-bit CRC
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*/
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/*---------------------------------------------------------------------------*/
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#include "sys/cc.h"
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/*---------------------------------------------------------------------------*/
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#include <ti/devices/DeviceFamily.h>
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#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
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#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h)
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#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h)
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#include DeviceFamily_constructPath(rf_patches/rf_patch_cpe_multi_protocol.h)
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#include DeviceFamily_constructPath(rf_patches/rf_patch_rfe_genfsk.h)
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#include DeviceFamily_constructPath(rf_patches/rf_patch_mce_genfsk.h)
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#include <ti/drivers/rf/RF.h>
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/*---------------------------------------------------------------------------*/
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#include "prop-settings.h"
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/*---------------------------------------------------------------------------*/
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/* TI-RTOS RF Mode Object */
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RF_Mode rf_prop_mode =
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{
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.rfMode = RF_MODE_AUTO,
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.cpePatchFxn = &rf_patch_cpe_multi_protocol,
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.mcePatchFxn = &rf_patch_mce_genfsk,
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.rfePatchFxn = &rf_patch_rfe_genfsk,
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};
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/*---------------------------------------------------------------------------*/
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#if defined(DEVICE_CC1312R) || defined(DEVICE_CC1352R)
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/*
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* CMD_PROP_RADIO_DIV_SETUP must be configured with default TX power value
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* in the .txPower field. This depends on whether RF_CONF_TXPOWER_BOOST_MODE
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* is configured or not.
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*/
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#if RF_CONF_TXPOWER_BOOST_MODE
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#define DEFAULT_TX_POWER 0x9F3F /* 14 dBm */
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#else
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#define DEFAULT_TX_POWER 0xCC14 /* 12.5 dBm (rounded up to 13 dBm) */
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#endif
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/*---------------------------------------------------------------------------*/
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/* Overrides for CMD_PROP_RADIO_DIV_SETUP */
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uint32_t rf_prop_overrides[] CC_ALIGN(4) =
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{
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/* override_use_patch_prop_genfsk.xml */
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MCE_RFE_OVERRIDE(1,0,0,1,0,0), /* PHY: Use MCE RAM patch, RFE RAM patch */
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/* override_synth_prop_863_930_div5.xml */
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(uint32_t)0x02400403, /* Synth: Use 48 MHz crystal as synth clock, enable extra PLL filtering */
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(uint32_t)0x00068793, /* Synth: Set minimum RTRIM to 6 */
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(uint32_t)0x001C8473, /* Synth: Configure extra PLL filtering */
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(uint32_t)0x00088433, /* Synth: Configure extra PLL filtering */
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(uint32_t)0x000684A3, /* Synth: Set Fref to 4 MHz */
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HW32_ARRAY_OVERRIDE(0x4004,1), /* Synth: Configure faster calibration */
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(uint32_t)0x180C0618, /* Synth: Configure faster calibration */
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(uint32_t)0xC00401A1, /* Synth: Configure faster calibration */
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(uint32_t)0x00010101, /* Synth: Configure faster calibration */
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(uint32_t)0xC0040141, /* Synth: Configure faster calibration */
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(uint32_t)0x00214AD3, /* Synth: Configure faster calibration */
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/* Synth: Decrease synth programming time-out by 90 us from default */
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(uint32_t)0x02980243, /* (0x0298 RAT ticks = 166 us) */
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(uint32_t)0x0A480583, /* Synth: Set loop bandwidth after lock to 20 kHz */
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(uint32_t)0x7AB80603, /* Synth: Set loop bandwidth after lock to 20 kHz */
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(uint32_t)0x00000623, /* Synth: Set loop bandwidth after lock to 20 kHz */
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/* override_phy_tx_pa_ramp_genfsk_hpa.xml */
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ADI_HALFREG_OVERRIDE(0,16,0x8,0x8), /* Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[3]=1) */
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ADI_HALFREG_OVERRIDE(0,17,0x1,0x1), /* Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4]=1) */
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/* override_phy_rx_frontend_genfsk.xml */
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HW_REG_OVERRIDE(0x609C,0x001A), /* Rx: Set AGC reference level to 0x1A (default: 0x2E) */
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(uint32_t)0x00018883, /* Rx: Set LNA bias current offset to adjust +1 (default: 0) */
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(uint32_t)0x000288A3, /* Rx: Set RSSI offset to adjust reported RSSI by -2 dB (default: 0) */
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/* override_phy_rx_aaf_bw_0xd.xml */
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/* Rx: Set anti-aliasing filter bandwidth to 0xD */
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ADI_HALFREG_OVERRIDE(0,61,0xF,0xD), /* (in ADI0, set IFAMPCTL3[7:4]=0xD) */
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#if RF_CONF_TXPOWER_BOOST_MODE
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/* TX power override */
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/* DC/DC regulator: In Tx with 14 dBm PA setting, */
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/* use DCDCCTL5[3:0]=0xF (DITHER_EN=1 and IPEAK=7). */
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(uint32_t)0xFFFC08C3, /* In Rx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). */
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/* Tx: Set PA trim to max to maximize its output power */
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ADI_REG_OVERRIDE(0,12,0xF8), /* (in ADI0, set PACTL0=0xF8) */
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#else
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/* TX power override */
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/* DC/DC regulator: */
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/* In Tx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). */
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(uint32_t)0xFCFC08C3, /* In Rx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). */
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#endif
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(uint32_t)0xFFFFFFFF,
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};
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#endif /* defined(DEVICE_CC1312R) || defined(DEVICE_CC1352R) */
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/*---------------------------------------------------------------------------*/
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#if defined(DEVICE_CC1352P)
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#if RF_CONF_TXPOWER_HIGH_PA
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/*
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* CMD_PROP_RADIO_DIV_SETUP must be configured with default TX power value
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* in the .txPower field. For High PA, this must be 0xFFFF.
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*/
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#define DEFAULT_TX_POWER 0xFFFF /* High PA */
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/*---------------------------------------------------------------------------*/
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/* Overrides for CMD_PROP_RADIO_DIV_SETUP with high PA */
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uint32_t rf_prop_overrides[] CC_ALIGN(4) =
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{
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/* override_use_patch_prop_genfsk.xml */
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MCE_RFE_OVERRIDE(1,0,0,1,0,0), /* PHY: Use MCE RAM patch, RFE RAM patch */
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/* override_synth_prop_863_930_div5.xml */
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(uint32_t)0x02400403, /* Synth: Use 48 MHz crystal as synth clock, enable extra PLL filtering */
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(uint32_t)0x00068793, /* Synth: Set minimum RTRIM to 6 */
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(uint32_t)0x001C8473, /* Synth: Configure extra PLL filtering */
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(uint32_t)0x00088433, /* Synth: Configure extra PLL filtering */
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(uint32_t)0x000684A3, /* Synth: Set Fref to 4 MHz */
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HW32_ARRAY_OVERRIDE(0x4004,1), /* Synth: Configure faster calibration */
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(uint32_t)0x180C0618, /* Synth: Configure faster calibration */
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(uint32_t)0xC00401A1, /* Synth: Configure faster calibration */
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(uint32_t)0x00010101, /* Synth: Configure faster calibration */
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(uint32_t)0xC0040141, /* Synth: Configure faster calibration */
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(uint32_t)0x00214AD3, /* Synth: Configure faster calibration */
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/* Synth: Decrease synth programming time-out by 90 us */
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(uint32_t)0x02980243, /* from default (0x0298 RAT ticks = 166 us) */
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(uint32_t)0x0A480583, /* Synth: Set loop bandwidth after lock to 20 kHz */
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(uint32_t)0x7AB80603, /* Synth: Set loop bandwidth after lock to 20 kHz */
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(uint32_t)0x00000623, /* Synth: Set loop bandwidth after lock to 20 kHz */
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/* override_phy_tx_pa_ramp_genfsk_hpa.xml */
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/* Tx: Configure PA ramping, set wait time before turning off */
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HW_REG_OVERRIDE(0x6028,0x002F), /* (0x2F ticks of 16/24 us = 31.3 us). */
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ADI_HALFREG_OVERRIDE(0,16,0x8,0x8), /* Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[3]=1) */
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ADI_HALFREG_OVERRIDE(0,17,0x1,0x1), /* Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4]=1) */
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/* override_phy_rx_frontend_genfsk.xml */
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HW_REG_OVERRIDE(0x609C,0x001A), /* Rx: Set AGC reference level to 0x1A (default: 0x2E) */
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(uint32_t)0x00018883, /* Rx: Set LNA bias current offset to adjust +1 (default: 0) */
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(uint32_t)0x000288A3, /* Rx: Set RSSI offset to adjust reported RSSI by -2 dB (default: 0) */
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/* override_phy_rx_aaf_bw_0xd.xml */
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/* Rx: Set anti-aliasing filter bandwidth to 0xD */
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ADI_HALFREG_OVERRIDE(0,61,0xF,0xD), /* (in ADI0, set IFAMPCTL3[7:4]=0xD) */
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/* TX power override */
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/* DC/DC regulator: */
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/* In Tx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). */
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(uint32_t)0xFCFC08C3, /* In Rx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). */
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(uint32_t)0x82A86C2B, /* txHighPA=0x20AA1B */
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(uint32_t)0xFFFFFFFF,
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};
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#else
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/*---------------------------------------------------------------------------*/
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/*
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* CMD_PROP_RADIO_DIV_SETUP must be configured with default TX power value
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* in the .txPower field. This depends on whether RF_CONF_TXPOWER_BOOST_MODE
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* is configured or not.
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*/
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#if RF_CONF_TXPOWER_BOOST_MODE
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#define DEFAULT_TX_POWER 0x013F /* 13.5 dBm (rounded up to 14 dBm) */
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#else
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#define DEFAULT_TX_POWER 0x803F /* 12 dBm */
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#endif
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/*---------------------------------------------------------------------------*/
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/* Overrides for CMD_PROP_RADIO_DIV_SETUP with defualt PA */
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uint32_t rf_prop_overrides[] CC_ALIGN(4) =
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{
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/* override_use_patch_prop_genfsk.xml */
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MCE_RFE_OVERRIDE(1,0,0,1,0,0), /* PHY: Use MCE RAM patch, RFE RAM patch */
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/* override_synth_prop_863_930_div5.xml */
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(uint32_t)0x02400403, /* Synth: Use 48 MHz crystal as synth clock, enable extra PLL filtering */
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(uint32_t)0x00068793, /* Synth: Set minimum RTRIM to 6 */
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(uint32_t)0x001C8473, /* Synth: Configure extra PLL filtering */
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(uint32_t)0x00088433, /* Synth: Configure extra PLL filtering */
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(uint32_t)0x000684A3, /* Synth: Set Fref to 4 MHz */
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HW32_ARRAY_OVERRIDE(0x4004,1), /* Synth: Configure faster calibration */
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(uint32_t)0x180C0618, /* Synth: Configure faster calibration */
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(uint32_t)0xC00401A1, /* Synth: Configure faster calibration */
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(uint32_t)0x00010101, /* Synth: Configure faster calibration */
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(uint32_t)0xC0040141, /* Synth: Configure faster calibration */
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(uint32_t)0x00214AD3, /* Synth: Configure faster calibration */
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/* Synth: Decrease synth programming time-out by 90 us from default */
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(uint32_t)0x02980243, /* (0x0298 RAT ticks = 166 us) */
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(uint32_t)0x0A480583, /* Synth: Set loop bandwidth after lock to 20 kHz */
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(uint32_t)0x7AB80603, /* Synth: Set loop bandwidth after lock to 20 kHz */
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(uint32_t)0x00000623, /* Synth: Set loop bandwidth after lock to 20 kHz */
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/* override_phy_tx_pa_ramp_genfsk_hpa.xml */
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/* Tx: Configure PA ramping, set wait time before turning off */
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HW_REG_OVERRIDE(0x6028,0x002F), /* (0x2F ticks of 16/24 us = 31.3 us). */
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ADI_HALFREG_OVERRIDE(0,16,0x8,0x8), /* Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[3]=1) */
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ADI_HALFREG_OVERRIDE(0,17,0x1,0x1), /* Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4]=1) */
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/* override_phy_rx_frontend_genfsk.xml */
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HW_REG_OVERRIDE(0x609C,0x001A), /* Rx: Set AGC reference level to 0x1A (default: 0x2E) */
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(uint32_t)0x00018883, /* Rx: Set LNA bias current offset to adjust +1 (default: 0) */
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(uint32_t)0x000288A3, /* Rx: Set RSSI offset to adjust reported RSSI by -2 dB (default: 0) */
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/* override_phy_rx_aaf_bw_0xd.xml */
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/* Rx: Set anti-aliasing filter bandwidth to 0xD */
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ADI_HALFREG_OVERRIDE(0,61,0xF,0xD), /* (in ADI0, set IFAMPCTL3[7:4]=0xD) */
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#if RF_CONF_TXPOWER_BOOST_MODE
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/* TX power override */
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/* DC/DC regulator: In Tx with 14 dBm PA setting, */
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/* use DCDCCTL5[3:0]=0xF (DITHER_EN=1 and IPEAK=7). */
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(uint32_t)0xFFFC08C3, /* In Rx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). */
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/* Tx: Set PA trim to max to maximize its output power */
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ADI_REG_OVERRIDE(0,12,0xF8), /* (in ADI0, set PACTL0=0xF8) */
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#else
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/* TX power override */
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/* DC/DC regulator: */
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/* In Tx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). */
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(uint32_t)0xFCFC08C3, /* In Rx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). */
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#endif
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(uint32_t)0xFFFFFFFF,
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};
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#endif /* RF_CONF_TXPOWER_HIGH_PA */
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#endif /* defined(DEVICE_CC1352P) */
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/*---------------------------------------------------------------------------*/
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/* CMD_PROP_RADIO_DIV_SETUP: Proprietary Mode Radio Setup Command for All Frequency Bands */
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rfc_CMD_PROP_RADIO_DIV_SETUP_t rf_cmd_prop_radio_div_setup =
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{
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.commandNo = CMD_PROP_RADIO_DIV_SETUP,
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.status = IDLE,
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.pNextOp = 0,
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.startTime = 0x00000000,
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.startTrigger.triggerType = TRIG_NOW,
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.startTrigger.bEnaCmd = 0x0,
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.startTrigger.triggerNo = 0x0,
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.startTrigger.pastTrig = 0x0,
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.condition.rule = COND_NEVER,
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.condition.nSkip = 0x0,
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.modulation.modType = 0x1,
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.modulation.deviation = 0x64,
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.modulation.deviationStepSz = 0x0,
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.symbolRate.preScale = 0xF,
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.symbolRate.rateWord = 0x8000,
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.symbolRate.decimMode = 0x0,
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.rxBw = 0x52,
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.preamConf.nPreamBytes = 0x7,
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.preamConf.preamMode = 0x0,
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.formatConf.nSwBits = 0x18,
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.formatConf.bBitReversal = 0x0,
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.formatConf.bMsbFirst = 0x1,
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.formatConf.fecMode = 0x0,
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.formatConf.whitenMode = 0x7,
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.config.frontEndMode = 0x0, /* set by driver */
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.config.biasMode = 0x0, /* set by driver */
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.config.analogCfgMode = 0x0,
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.config.bNoFsPowerUp = 0x0,
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.txPower = DEFAULT_TX_POWER,
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.pRegOverride = rf_prop_overrides,
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.centerFreq = 0x0393, /* set by driver */
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.intFreq = 0x8000, /* set by driver */
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.loDivider = 0x05, /* set by driver */
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};
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/*---------------------------------------------------------------------------*/
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/* CMD_FS: Frequency Synthesizer Programming Command */
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rfc_CMD_FS_t rf_cmd_prop_fs =
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{
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.commandNo = CMD_FS,
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.status = IDLE,
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.pNextOp = 0,
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.startTime = 0x00000000,
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.startTrigger.triggerType = TRIG_NOW,
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.startTrigger.bEnaCmd = 0x0,
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.startTrigger.triggerNo = 0x0,
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.startTrigger.pastTrig = 0x0,
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.condition.rule = COND_NEVER,
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.condition.nSkip = 0x0,
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.frequency = 0x0393, /* set by driver */
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.fractFreq = 0x0000, /* set by driver */
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.synthConf.bTxMode = 0x0,
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.synthConf.refFreq = 0x0,
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.__dummy0 = 0x00,
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.__dummy1 = 0x00,
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.__dummy2 = 0x00,
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.__dummy3 = 0x0000,
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};
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/*---------------------------------------------------------------------------*/
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/* CMD_PROP_TX_ADV: Proprietary Mode Advanced Transmit Command */
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rfc_CMD_PROP_TX_ADV_t rf_cmd_prop_tx_adv =
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{
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.commandNo = CMD_PROP_TX_ADV,
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.status = IDLE,
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.pNextOp = 0,
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.startTime = 0x00000000,
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.startTrigger.triggerType = TRIG_NOW,
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.startTrigger.bEnaCmd = 0x0,
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.startTrigger.triggerNo = 0x0,
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.startTrigger.pastTrig = 0x0,
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.condition.rule = COND_NEVER,
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.condition.nSkip = 0x0,
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.pktConf.bFsOff = 0x0,
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.pktConf.bUseCrc = 0x1,
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.pktConf.bCrcIncSw = 0x0,
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.pktConf.bCrcIncHdr = 0x0,
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.numHdrBits = 0x10,
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.pktLen = 0x0, /* set by driver */
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.startConf.bExtTxTrig = 0x0,
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|
.startConf.inputMode = 0x0,
|
|
.startConf.source = 0x0,
|
|
.preTrigger.triggerType = TRIG_REL_START,
|
|
.preTrigger.bEnaCmd = 0x0,
|
|
.preTrigger.triggerNo = 0x0,
|
|
.preTrigger.pastTrig = 0x1,
|
|
.preTime = 0x00000000,
|
|
.syncWord = 0x0055904E,
|
|
.pPkt = 0, /* set by driver */
|
|
};
|
|
/*---------------------------------------------------------------------------*/
|
|
/* CMD_PROP_RX_ADV: Proprietary Mode Advanced Receive Command */
|
|
rfc_CMD_PROP_RX_ADV_t rf_cmd_prop_rx_adv =
|
|
{
|
|
.commandNo = CMD_PROP_RX_ADV,
|
|
.status = IDLE,
|
|
.pNextOp = 0,
|
|
.startTime = 0x00000000,
|
|
.startTrigger.triggerType = TRIG_NOW,
|
|
.startTrigger.bEnaCmd = 0x0,
|
|
.startTrigger.triggerNo = 0x0,
|
|
.startTrigger.pastTrig = 0x0,
|
|
.condition.rule = COND_NEVER,
|
|
.condition.nSkip = 0x0,
|
|
.pktConf.bFsOff = 0x0,
|
|
.pktConf.bRepeatOk = 0x1,
|
|
.pktConf.bRepeatNok = 0x1,
|
|
.pktConf.bUseCrc = 0x1,
|
|
.pktConf.bCrcIncSw = 0x0,
|
|
.pktConf.bCrcIncHdr = 0x0,
|
|
.pktConf.endType = 0x0,
|
|
.pktConf.filterOp = 0x1,
|
|
.rxConf.bAutoFlushIgnored = 0x1,
|
|
.rxConf.bAutoFlushCrcErr = 0x1,
|
|
.rxConf.bIncludeHdr = 0x0,
|
|
.rxConf.bIncludeCrc = 0x0,
|
|
.rxConf.bAppendRssi = 0x1,
|
|
.rxConf.bAppendTimestamp = 0x0,
|
|
.rxConf.bAppendStatus = 0x1,
|
|
.syncWord0 = 0x0055904E,
|
|
.syncWord1 = 0x00000000,
|
|
.maxPktLen = 0x0, /* set by driver */
|
|
.hdrConf.numHdrBits = 0x10,
|
|
.hdrConf.lenPos = 0x0,
|
|
.hdrConf.numLenBits = 0x0B,
|
|
.addrConf.addrType = 0x0,
|
|
.addrConf.addrSize = 0x0,
|
|
.addrConf.addrPos = 0x0,
|
|
.addrConf.numAddr = 0x0,
|
|
.lenOffset = 0xFC,
|
|
.endTrigger.triggerType = TRIG_NEVER,
|
|
.endTrigger.bEnaCmd = 0x0,
|
|
.endTrigger.triggerNo = 0x0,
|
|
.endTrigger.pastTrig = 0x0,
|
|
.endTime = 0x00000000,
|
|
.pAddr = 0, /* set by driver */
|
|
.pQueue = 0, /* set by driver */
|
|
.pOutput = 0, /* set by driver */
|
|
};
|
|
/*---------------------------------------------------------------------------*/
|