85 lines
3.4 KiB
C
85 lines
3.4 KiB
C
/* Timer registers are all 16-bit wide with 16-bit access only */
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#define TMR_OFFSET (0x20)
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#define TMR_BASE (0x80007000)
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#define TMR0_BASE (TMR_BASE)
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#define TMR1_BASE (TMR_BASE + TMR_OFFSET*1)
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#define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
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#define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
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#define TMR_REGOFF_COMP1 (0x0)
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#define TMR_REGOFF_COMP2 (0x2)
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#define TMR_REGOFF_CAPT (0x4)
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#define TMR_REGOFF_LOAD (0x6)
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#define TMR_REGOFF_HOLD (0x8)
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#define TMR_REGOFF_CNTR (0xa)
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#define TMR_REGOFF_CTRL (0xc)
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#define TMR_REGOFF_SCTRL (0xe)
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#define TMR_REGOFF_CMPLD1 (0x10)
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#define TMR_REGOFF_CMPLD2 (0x12)
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#define TMR_REGOFF_CSCTRL (0x14)
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#define TMR_REGOFF_ENBL (0x1e)
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/* one enable register to rule them all */
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#define TMR_ENBL TMR0_BASE + TMR_REGOFF_ENBL
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/* Timer 0 registers */
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#define TMR0_COMP1 (TMR0_BASE + TMR_REGOFF_COMP1)
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#define TMR0_COMP_UP TMR0_COMP1
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#define TMR0_COMP2 (TMR0_BASE + TMR_REGOFF_COMP2)
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#define TMR0_COMP_DOWN TMR0_COMP2
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#define TMR0_CAPT (TMR0_BASE + TMR_REGOFF_CAPT)
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#define TMR0_LOAD (TMR0_BASE + TMR_REGOFF_LOAD)
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#define TMR0_HOLD (TMR0_BASE + TMR_REGOFF_HOLD)
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#define TMR0_CNTR (TMR0_BASE + TMR_REGOFF_CTRL)
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#define TMR0_CTRL (TMR0_BASE + TMR_REGOFF_CTRL)
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#define TMR0_SCTRL (TMR0_BASE + TMR_REGOFF_SCTRL)
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#define TMR0_CMPLD1 (TMR0_BASE + TMR_REGOFF_CMPLD1)
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#define TMR0_CMPLD2 (TMR0_BASE + TMR_REGOFF_CMPLD2)
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#define TMR0_CSCTRL (TMR0_BASE + TMR_REGOFF_CSCTRL)
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/* Timer 1 registers */
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#define TMR1_COMP1 (TMR1_BASE + TMR_REGOFF_COMP1)
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#define TMR1_COMP_UP TMR1_COMP1
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#define TMR1_COMP2 (TMR1_BASE + TMR_REGOFF_COMP2)
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#define TMR1_COMP_DOWN TMR1_COMP2
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#define TMR1_CAPT (TMR1_BASE + TMR_REGOFF_CAPT)
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#define TMR1_LOAD (TMR1_BASE + TMR_REGOFF_LOAD)
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#define TMR1_HOLD (TMR1_BASE + TMR_REGOFF_HOLD)
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#define TMR1_CNTR (TMR1_BASE + TMR_REGOFF_CTRL)
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#define TMR1_CTRL (TMR1_BASE + TMR_REGOFF_CTRL)
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#define TMR1_SCTRL (TMR1_BASE + TMR_REGOFF_SCTRL)
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#define TMR1_CMPLD1 (TMR1_BASE + TMR_REGOFF_CMPLD1)
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#define TMR1_CMPLD2 (TMR1_BASE + TMR_REGOFF_CMPLD2)
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#define TMR1_CSCTRL (TMR1_BASE + TMR_REGOFF_CSCTRL)
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/* Timer 2 registers */
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#define TMR2_COMP1 (TMR2_BASE + TMR_REGOFF_COMP1)
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#define TMR2_COMP_UP TMR2_COMP1
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#define TMR2_COMP2 (TMR2_BASE + TMR_REGOFF_COMP2)
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#define TMR2_COMP_DOWN TMR2_COMP2
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#define TMR2_CAPT (TMR2_BASE + TMR_REGOFF_CAPT)
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#define TMR2_LOAD (TMR2_BASE + TMR_REGOFF_LOAD)
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#define TMR2_HOLD (TMR2_BASE + TMR_REGOFF_HOLD)
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#define TMR2_CNTR (TMR2_BASE + TMR_REGOFF_CTRL)
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#define TMR2_CTRL (TMR2_BASE + TMR_REGOFF_CTRL)
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#define TMR2_SCTRL (TMR2_BASE + TMR_REGOFF_SCTRL)
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#define TMR2_CMPLD1 (TMR2_BASE + TMR_REGOFF_CMPLD1)
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#define TMR2_CMPLD2 (TMR2_BASE + TMR_REGOFF_CMPLD2)
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#define TMR2_CSCTRL (TMR2_BASE + TMR_REGOFF_CSCTRL)
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/* Timer 3 registers */
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#define TMR3_COMP1 (TMR3_BASE + TMR_REGOFF_COMP1)
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#define TMR3_COMP_UP TMR3_COMP1
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#define TMR3_COMP2 (TMR3_BASE + TMR_REGOFF_COMP2)
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#define TMR3_COMP_DOWN TMR3_COMP2
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#define TMR3_CAPT (TMR3_BASE + TMR_REGOFF_CAPT)
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#define TMR3_LOAD (TMR3_BASE + TMR_REGOFF_LOAD)
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#define TMR3_HOLD (TMR3_BASE + TMR_REGOFF_HOLD)
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#define TMR3_CNTR (TMR3_BASE + TMR_REGOFF_CTRL)
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#define TMR3_CTRL (TMR3_BASE + TMR_REGOFF_CTRL)
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#define TMR3_SCTRL (TMR3_BASE + TMR_REGOFF_SCTRL)
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#define TMR3_CMPLD1 (TMR3_BASE + TMR_REGOFF_CMPLD1)
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#define TMR3_CMPLD2 (TMR3_BASE + TMR_REGOFF_CMPLD2)
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#define TMR3_CSCTRL (TMR3_BASE + TMR_REGOFF_CSCTRL)
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