182 lines
6.7 KiB
Plaintext
182 lines
6.7 KiB
Plaintext
//------------------------------------------------------------------------------
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// @file hal/micro/cortexm3/spmr.s79
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// @brief SPMR (Special Purpose Mask Registers) manipulation routines.
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//
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// Since the compiler does not provide low level intrinsic functions for some
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// required operations, this file maintains the small set of assembly code
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// needed to manipulate the Special Purpose Mask Registers.
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//
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// While it is possible to add this functionality as inline assembly in C files,
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// IAR highly recommends against this due to not only code being fragile in its
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// surroundings, but it also negates the possibility of size optimization.
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//
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// NOTE: This file looks more complicated than it really is. It was originally
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// generated by writing a C file and having the compiler generate the
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// corresponding assembly file. This is where all the CFI (Call Frame
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// Information) expressions came from. The CFI information enables proper debug
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// backtrace ability. The pieces to pay attention to are the actual funtions
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// near the end.
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//
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// * <!--(C) COPYRIGHT 2010 STMicroelectronics. All rights reserved. -->
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//------------------------------------------------------------------------------
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#include "compiler/asm.h"
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// NOTE!! IF THIS VALUE IS CHANGED, NVIC-CONFIG.H MUST ALSO BE UPDATED
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#define INTERRUPTS_DISABLED_PRIORITY (12 << 3)
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__EXPORT__ _readBasePri
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__EXPORT__ _writeBasePri
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__EXPORT__ _disableBasePri
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__EXPORT__ _basePriIsDisabled
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__EXPORT__ _enableBasePri
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__EXPORT__ _setPriMask
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__EXPORT__ _clearPriMask
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__EXPORT__ _executeBarrierInstructions
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//------------------------------------------------------------------------------
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// uint8_t _readBasePri(void)
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//
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// Read and return the BASEPRI value.
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//
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//------------------------------------------------------------------------------
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__CODE__
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__THUMB__
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__CFI__(Block cfiBlock0 Using cfiCommon0)
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__CFI__(Function _readBasePri)
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_readBasePri:
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MRS R0, BASEPRI // read current BASEPRI
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BX LR
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__CFI__(EndBlock cfiBlock0)
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//------------------------------------------------------------------------------
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// void _writeBasePri(uint8_t priority)
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//
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// Write BASEPRI with the passed value to obtain the proper preemptive priority
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// group masking. Note that the value passed must have been left shifted by 3
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// to be properly aligned in the BASEPRI register.
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// (Refer to nvic-config.h for the PRIGROUP table.)
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//
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//------------------------------------------------------------------------------
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__CODE__
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__THUMB__
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__CFI__(Block cfiBlock1 Using cfiCommon0)
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__CFI__(Function _writeBasePri)
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_writeBasePri:
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MSR BASEPRI, R0 // load BASEPRI from variable (R0)
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BX LR
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__CFI__(EndBlock cfiBlock1)
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//------------------------------------------------------------------------------
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// uint8_t _disableBasePri(void)
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//
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// Set BASEPRI to mask out interrupts but allow faults. It returns the value
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// BASEPRI had when it was called.
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//
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//------------------------------------------------------------------------------
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__CODE__
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__THUMB__
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__CFI__(Block cfiBlock2 Using cfiCommon0)
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__CFI__(Function _disableBasePri)
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_disableBasePri:
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MRS R0, BASEPRI // read current BASEPRI
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LDR R1, =INTERRUPTS_DISABLED_PRIORITY // disable ints, allow faults
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MSR BASEPRI, R1
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BX LR
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__CFI__(EndBlock cfiBlock2)
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//------------------------------------------------------------------------------
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// boolean _basePriIsDisabled(void)
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//
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// Compare BASEPRI to the priority used to disable interrupts (but not faults).
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// Return TRUE if the priority is higher or equal to that.
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//
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//------------------------------------------------------------------------------
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__CODE__
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__THUMB__
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__CFI__(Block cfiBlock3 Using cfiCommon0)
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__CFI__(Function _basePriIsDisabled)
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_basePriIsDisabled:
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MRS R0, BASEPRI // read current BASEPRI
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CMP R0, #INTERRUPTS_DISABLED_PRIORITY
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ITE lt
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LDRLT R0, =0
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LDRGE R0, =1
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BX LR
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__CFI__(EndBlock cfiBlock3)
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//------------------------------------------------------------------------------
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// void _enableBasePri(void)
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//
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// Set BASEPRI to 0, which disables it from masking any interrupts.
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//
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//------------------------------------------------------------------------------
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__CODE__
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__THUMB__
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__CFI__(Block cfiBlock4 Using cfiCommon0)
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__CFI__(Function _enableBasePri)
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_enableBasePri:
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LDR R1, = 0 // zero disables BASEPRI masking
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MSR BASEPRI, R1
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BX LR
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__CFI__(EndBlock cfiBlock4)
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//------------------------------------------------------------------------------
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// void _setPriMask(void)
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//
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// Set the 1-bit PRIMASK register, which sets the base priority to 0. This
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// locks out all interrupts and configurable faults (usage, memory management
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// and bus faults).
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//
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// Note: generally speaking PRIMASK should not be set because faults should
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// be enabled even when interrupts are disabled. If they are not enabled,
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// a fault will immediately escalate to a hard fault.
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//
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//------------------------------------------------------------------------------
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__CODE__
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__THUMB__
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__CFI__(Block cfiBlock5 Using cfiCommon0)
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__CFI__(Function _setPriMask)
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_setPriMask:
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CPSID i
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BX LR
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__CFI__(EndBlock cfiBlock5)
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//------------------------------------------------------------------------------
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// void _clearPriMask(void)
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//
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// Clears the 1-bit PRIMASK register, which allows the BASEPRI value to
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// mask interrupts (if non-zero).
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//
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//------------------------------------------------------------------------------
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__CODE__
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__THUMB__
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__CFI__(Block cfiBlock6 Using cfiCommon0)
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__CFI__(Function _clearPriMask)
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_clearPriMask:
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CPSIE i
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BX LR
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__CFI__(EndBlock cfiBlock6)
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//------------------------------------------------------------------------------
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// void _executeBarrierInstructions(void)
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//
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//A utility function for inserting barrier instructions. These
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//instructions should be used whenever the MPU is enabled or disabled so
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//that all memory/instruction accesses can complete before the MPU changes
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//state.
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//
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//------------------------------------------------------------------------------
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__CODE__
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__THUMB__
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__CFI__(Block cfiBlock7 Using cfiCommon0)
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__CFI__(Function _executeBarrierInstructions)
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_executeBarrierInstructions:
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DMB
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DSB
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ISB
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BX LR
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__CFI__(EndBlock cfiBlock7)
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__END__
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