122 lines
3.8 KiB
C
122 lines
3.8 KiB
C
/** @file micro-common.c
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* @brief STM32W108 micro specific HAL functions common to
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* full and minimal hal
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*
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*
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* <!--(C) COPYRIGHT 2010 STMicroelectronics. All rights reserved. -->
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*/
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#include PLATFORM_HEADER
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#include BOARD_HEADER
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#include "error.h"
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#include "hal/micro/micro-common.h"
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#include "hal/micro/cortexm3/micro-common.h"
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void halInternalEnableWatchDog(void)
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{
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//Just to be on the safe side, restart the watchdog before enabling it
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WDOG_RESET = 1;
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WDOG_KEY = 0xEABE;
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WDOG_CFG = WDOG_ENABLE;
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}
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void halInternalResetWatchDog(void)
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{
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//Writing any value will restart the watchdog
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WDOG_RESET = 1;
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}
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void halInternalDisableWatchDog(int8u magicKey)
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{
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if (magicKey == MICRO_DISABLE_WATCH_DOG_KEY) {
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WDOG_KEY = 0xDEAD;
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WDOG_CFG = WDOG_DISABLE;
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}
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}
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boolean halInternalWatchDogEnabled(void)
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{
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if(WDOG_CFG&WDOG_ENABLE) {
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return TRUE;
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} else {
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return FALSE;
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}
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}
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void halGpioConfig(int32u io, int32u config)
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{
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static volatile int32u *const configRegs[] =
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{ (volatile int32u *)GPIO_PACFGL_ADDR,
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(volatile int32u *)GPIO_PACFGH_ADDR,
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(volatile int32u *)GPIO_PBCFGL_ADDR,
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(volatile int32u *)GPIO_PBCFGH_ADDR,
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(volatile int32u *)GPIO_PCCFGL_ADDR,
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(volatile int32u *)GPIO_PCCFGH_ADDR };
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int32u portcfg;
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portcfg = *configRegs[io/4]; // get current config
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portcfg = portcfg & ~((0xF)<<((io&3)*4)); // mask out config of this pin
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*configRegs[io/4] = portcfg | (config <<((io&3)*4));
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}
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void halGpioSet(int32u gpio, boolean value)
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{
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if(gpio/8 < 3) {
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if (value) {
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*((volatile int32u *)(GPIO_PxSET_BASE+(GPIO_Px_OFFSET*(gpio/8)))) = BIT(gpio&7);
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} else {
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*((volatile int32u *)(GPIO_PxCLR_BASE+(GPIO_Px_OFFSET*(gpio/8)))) = BIT(gpio&7);
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}
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}
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}
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int16u halInternalStartSystemTimer(void)
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{
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//Since the SleepTMR is the only timer maintained during deep sleep, it is
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//used as the System Timer (RTC). We maintain a 32 bit hardware timer
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//configured for a tick value time of 1024 ticks/second (0.9765625 ms/tick)
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//using either the 10 kHz internal SlowRC clock divided and calibrated to
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//1024 Hz or the external 32.768 kHz crystal divided to 1024 Hz.
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//With a tick time of ~1ms, this 32bit timer will wrap after ~48.5 days.
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//disable top-level interrupt while configuring
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INT_CFGCLR = INT_SLEEPTMR;
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#ifdef ENABLE_OSC32K
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#ifdef DIGITAL_OSC32_EXT
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//Disable both OSC32K and SLOWRC if using external digital clock input
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SLEEPTMR_CLKEN = 0;
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#else//!DIGITAL_OSC32_EXT
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//Enable the 32kHz XTAL (and disable SlowRC since it is not needed)
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SLEEPTMR_CLKEN = SLEEPTMR_CLK32KEN;
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#endif
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//Sleep timer configuration is the same for crystal and external clock
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SLEEPTMR_CFG = (SLEEPTMR_ENABLE | //enable TMR
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(0 << SLEEPTMR_DBGPAUSE_BIT)| //TMR paused when halted
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(5 << SLEEPTMR_CLKDIV_BIT) | //divide down to 1024Hz
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(1 << SLEEPTMR_CLKSEL_BIT)) ; //select XTAL
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#else //!ENABLE_OSC32K
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//Enable the SlowRC (and disable 32kHz XTAL since it is not needed)
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SLEEPTMR_CLKEN = SLEEPTMR_CLK10KEN;
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SLEEPTMR_CFG = (SLEEPTMR_ENABLE | //enable TMR
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(0 << SLEEPTMR_DBGPAUSE_BIT)| //TMR paused when halted
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(0 << SLEEPTMR_CLKDIV_BIT) | //already 1024Hz
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(0 << SLEEPTMR_CLKSEL_BIT)) ; //select SlowRC
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#ifndef DISABLE_RC_CALIBRATION
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halInternalCalibrateSlowRc(); //calibrate SlowRC to 1024Hz
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#endif//DISABLE_RC_CALIBRATION
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#endif//ENABLE_OSC32K
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//clear out any stale interrupts
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INT_SLEEPTMRFLAG = (INT_SLEEPTMRWRAP | INT_SLEEPTMRCMPA | INT_SLEEPTMRCMPB);
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//turn off second level interrupts. they will be enabled elsewhere as needed
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INT_SLEEPTMRCFG = INT_SLEEPTMRCFG_RESET;
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//enable top-level interrupt
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INT_CFGSET = INT_SLEEPTMR;
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return 0;
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}
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