2022-10-08 13:11:59 +00:00
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/**
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* @file main.c
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* @author giomba@glgprograms.it
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* @brief OSDY main.
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*
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* @copyright Copyright RetrOfficina GLG Programs (c) 2022
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*
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* Video image generator superimposition for analog PAL signals,
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* with Atmega328, for your retro OSD titles.
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*
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*/
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2021-07-03 13:02:01 +00:00
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#include "const.h"
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2022-10-08 13:11:59 +00:00
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#include <avr/interrupt.h>
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#include <avr/io.h>
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2021-07-03 14:42:32 +00:00
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#include <string.h>
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2021-07-03 13:02:01 +00:00
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2022-10-08 13:11:59 +00:00
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volatile uint16_t frame = 0;
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volatile uint16_t line = 0xfe;
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volatile uint8_t image = 0xff;
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2021-06-26 17:15:17 +00:00
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2021-06-26 20:34:22 +00:00
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ISR(INT0_vect, ISR_NAKED) {
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2022-10-08 13:11:59 +00:00
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// vertical sync interrupt
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asm("jmp int_vertical_sync");
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2021-06-26 21:42:23 +00:00
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}
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ISR(INT1_vect, ISR_NAKED) {
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2022-10-08 13:11:59 +00:00
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// horizontal sync interrupt
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asm("jmp int_horizontal_sync");
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2021-06-26 17:15:17 +00:00
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}
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2021-07-03 09:54:31 +00:00
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ISR(TIMER0_COMPA_vect, ISR_NAKED) {
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2022-10-08 13:11:59 +00:00
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// back porch timer interrupt
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asm("jmp int_timer_0");
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2021-07-03 09:54:31 +00:00
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}
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2021-07-03 13:02:01 +00:00
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2022-10-08 13:11:59 +00:00
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// external assembly main loop
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void main_asm(void);
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int main() {
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// port B, pin 4 and 5 as output, others as input
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DDRB |= 0x30;
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2021-07-03 13:44:01 +00:00
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2022-10-08 13:11:59 +00:00
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// set interrupt vectors at address 0x0, not bootloader
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// timing is important, see atmel datasheet
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_SFR_IO8(MCUCR) = (1 << IVCE);
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_SFR_IO8(MCUCR) = 0;
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EICRA = 0x0a; // external interrupt 0 and 1, falling edge
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EIMSK = 0x03; // external interrupt 0 and 1, mask enable
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TCCR0A = 0x02; // don't connect output pins to timer, CTC[1:0] mode
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TCCR0B = 0x01; // CTC[2] mode, no prescaler
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main_asm();
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}
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