something strange is happening

This commit is contained in:
giomba 2021-06-27 21:57:02 +02:00
parent 97e0ff26fa
commit 14fd0412d4
3 changed files with 62 additions and 61 deletions

4
const.h Normal file
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@ -0,0 +1,4 @@
#pragma once
#define VERTICAL_OFFSET 30

113
main.S
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@ -1,25 +1,27 @@
#include <avr/io.h> #include <avr/io.h>
#include "macro.h" #include "macro.h"
#include "const.h"
.data .data
vertical_offset:
.byte 0
status: frame:
.byte 0x0 .byte 0
offset:
.byte 78
line: line:
.word 0 .byte 0
.text .text
.global main_s .global main
main_s: main:
ldi r16, 0x30 ldi r16, 0x30 ; port B, pin 4 and 5 as output
sts DDRB, r16 sts DDRB, r16
ldi r16, (1 << IVCE) ; set vector at address 0x0 ; set interrupt vectors at address 0x0, not bootloader
; timing is important, see atmel datasheet
ldi r16, (1 << IVCE)
ldi r17, 0 ldi r17, 0
out IO(MCUCR), r16 out IO(MCUCR), r16
out IO(MCUCR), r17 out IO(MCUCR), r17
@ -30,44 +32,25 @@ main_s:
ldi r16, 0x3 ; external interrupt 0 and 1, mask enable ldi r16, 0x3 ; external interrupt 0 and 1, mask enable
sts EIMSK, r16 sts EIMSK, r16
sei sei ; global interrupt enable
again:
sbi IO(PORTB), 5
ldi r16, 0x1
sts status, r16
wait1:
ldi r16, 0xff
ldi r17, 0xff
ldi r18, 0xff
1: 1:
dec r16 sbi IO(PORTB), 5
brne 1b ldi r18, 0
dec r17 2:
brne 1b
dec r18 dec r18
brne 1b brne 2b
cbi IO(PORTB), 5 cbi IO(PORTB), 5
ldi r16, 0x0
sts status, r16
wait2: ldi r18, 0
ldi r16, 0xff 3:
ldi r17, 0xff
ldi r18, 0xff
1:
dec r16
brne 1b
dec r17
brne 1b
dec r18 dec r18
brne 1b brne 3b
jmp again rjmp 1b
jmp .
.global int_horizontal_sync .global int_horizontal_sync
int_horizontal_sync: int_horizontal_sync:
@ -75,26 +58,34 @@ int_horizontal_sync:
in r31, IO(SREG) ; status register in r31, IO(SREG) ; status register
push r31 push r31
#if 0
lds r31, vertical_offset
cpi r31, 0
breq enter1
dec r31
sts vertical_offset, r31
jmp int_horizontal_sync_end
enter1:
lds r31, line lds r31, line
cpi r31, 255 cpi r31, 0
brsh int_horizontal_sync_end breq int_horizontal_sync_end
inc r31 inc r31
sts line, r31 sts line, r31
lds r31, status lds r31, frame
cpi r31, 0 lsr r31
brne int_horizontal_sync_end lsr r31
breq 2f
lds r31, offset 1:
dec r31 dec r31
cpi r31, 1 brne 1b
brne 1f #endif
ldi r31, 140 ldi r31, 140
1: 1:
sts offset, r31
loop:
dec r31 dec r31
brne loop brne 1b
sbi IO(PORTB), 4 sbi IO(PORTB), 4
nop nop
@ -118,10 +109,22 @@ int_horizontal_sync_end:
.global int_vertical_sync .global int_vertical_sync
int_vertical_sync: int_vertical_sync:
push r31 push r31
ldi r31, 0 in r31, IO(SREG)
push r31
lds r31, frame
inc r31
sts frame, r31
ldi r31, 1
sts line, r31 sts line, r31
ldi r31, 140
sts offset, r31 ldi r31, VERTICAL_OFFSET
sts vertical_offset, r31
int_vertical_sync_end:
pop r31
out IO(SREG), r31
pop r31 pop r31
reti reti

6
main.c
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@ -1,9 +1,6 @@
#include <avr/io.h> #include <avr/io.h>
#include <avr/interrupt.h> #include <avr/interrupt.h>
void main_s(void);
ISR(INT0_vect, ISR_NAKED) { ISR(INT0_vect, ISR_NAKED) {
asm("jmp int_vertical_sync"); asm("jmp int_vertical_sync");
} }
@ -11,6 +8,3 @@ ISR(INT1_vect, ISR_NAKED) {
asm("jmp int_horizontal_sync"); asm("jmp int_horizontal_sync");
} }
int main() {
main_s();
}