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Dedicated module for VGA.

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This commit is contained in:
giomba 2022-12-03 20:52:47 +01:00
parent 74e5da5405
commit ac055b6673
4 changed files with 207 additions and 185 deletions
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1
CMakeLists.txt
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@ -20,6 +20,7 @@ add_executable(ceda2vga
src/main.c src/main.c
src/draw_demo.c src/draw_demo.c
src/framebuffer.c src/framebuffer.c
src/vga.c
) )
pico_generate_pio_header(ceda2vga pico_generate_pio_header(ceda2vga

193
src/main.c
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@ -8,10 +8,8 @@
*/ */
#include "hardware/clocks.h" #include "hardware/clocks.h"
#include "hardware/dma.h"
#include "hardware/pio.h"
#include "hardware/pll.h" #include "hardware/pll.h"
#include "hardware/structs/pio.h"
#include "pico/stdlib.h" #include "pico/stdlib.h"
#include <stdint.h> #include <stdint.h>
@ -19,66 +17,9 @@
#include <math.h> #include <math.h>
#include <stdlib.h> #include <stdlib.h>
#include "vga.pio.h"
#include "draw_demo.h" #include "draw_demo.h"
#include "framebuffer.h" #include "framebuffer.h"
#include "vga.h"
static void vga_pixel_program_init(PIO pio, uint sm, uint offset)
{
// config function automatically declared by SDK scripts
// based on the names given to programs in .pio
pio_sm_config config = vga_pixel_program_get_default_config(offset);
// destination pins for OUT instructions
sm_config_set_out_pins(&config, 22, 1);
sm_config_set_out_shift(&config, true, true, 0);
pio_gpio_init(pio, 22);
pio_sm_set_consecutive_pindirs(pio, sm, 22, 1, true);
sm_config_set_wrap(&config, offset + vga_pixel_wrap_target, offset + vga_pixel_wrap);
pio_sm_init(pio, sm, offset, &config);
pio_sm_set_clkdiv_int_frac(pio, sm, 1, 0);
pio_sm_set_enabled(pio, sm, true);
}
static void vga_hsync_program_init(PIO pio, uint sm, uint offset)
{
pio_sm_config config = vga_hsync_program_get_default_config(offset);
// destination pins for SET instructions
sm_config_set_set_pins(&config, 20, 1);
pio_gpio_init(pio, 20);
pio_sm_set_consecutive_pindirs(pio, sm, 20, 1, true);
sm_config_set_wrap(&config, offset + vga_hsync_wrap_target, offset + vga_hsync_wrap);
pio_sm_init(pio, sm, offset, &config);
pio_sm_set_clkdiv_int_frac(pio, sm, 1, 0);
pio->sm->shiftctrl = (1 << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB);
pio_sm_set_enabled(pio, sm, true);
}
static void vga_vsync_program_init(PIO pio, uint sm, uint offset)
{
pio_sm_config config = vga_vsync_program_get_default_config(offset);
// destination pins for SET instructions
sm_config_set_set_pins(&config, 21, 1);
pio_gpio_init(pio, 21);
pio_sm_set_consecutive_pindirs(pio, sm, 21, 1, true);
sm_config_set_wrap(&config, offset + vga_vsync_wrap_target, offset + vga_vsync_wrap);
pio_sm_init(pio, sm, offset, &config);
pio_sm_set_clkdiv_int_frac(pio, sm, 1, 0);
pio->sm->shiftctrl = (1 << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB);
pio_sm_set_enabled(pio, sm, true);
}
void setup_clocks(void) void setup_clocks(void)
{ {
@ -104,132 +45,14 @@ void setup_clocks(void)
clock_configure(clk_peri, 0, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, 126 * MHZ, 126 * MHZ); clock_configure(clk_peri, 0, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, 126 * MHZ, 126 * MHZ);
} }
static bool dma_ready = false;
static int dma_channel;
/**
* @brief Represents a program running on the SM of a PIO.
*
*/
typedef struct PIORun
{
PIO pio; //< executing PIO
uint offset; //< PIO memory offset for program
uint sm; //< executing SM
} PIORun;
static PIORun *vga_pixel_ptr = NULL;
static unsigned long int frame_counter = 0;
void dma_handler(void)
{
// acknoweledge DMA
dma_hw->ints0 = 1 << dma_channel;
}
void new_frame_handler(void)
{
if (vga_pixel_ptr && dma_ready)
{
// Explicitly put the first uint32_t word in the FIFO,
// because, when PIO pulls data for the first time,
// and its FIFO is empty, the DMA controller takes "a while"
// to put the first word and keep up with the transfer,
// making the whole frame a bit offset to the right.
// Since front porch is very short, even the smallest delay,
// may disrupt the timing.
// Also note: despite the "blocking put", when this interrupt
// is serviced, PIO FIFO is always empty, so in practice
// this will never block.
pio_sm_put_blocking(vga_pixel_ptr->pio, vga_pixel_ptr->sm, 0);
// Start DMA (but skip the initial word, which has been put manually)
dma_channel_set_read_addr(dma_channel, &frame[4], true);
}
frame_counter++;
pio_interrupt_clear(pio0_hw, 1);
}
int main() int main()
{ {
setup_clocks(); setup_clocks();
stdio_init_all(); stdio_init_all();
sleep_ms(1000);
draw_demo(); draw_demo();
// Running programs on PIO vga_machines_init();
PIORun vga_hsync, vga_vsync, vga_pixel;
vga_hsync.pio = vga_vsync.pio = vga_pixel.pio = pio0;
// Prepare frame interrupt
// Frame interrupt is asserted on PIO0 interrupt 1 by SM1
pio_set_irq1_source_enabled(vga_vsync.pio, pis_interrupt1,
true); // allow SM1 of PIO to fire the interrupt
irq_set_exclusive_handler(PIO0_IRQ_1, new_frame_handler); // set handler for IRQ1 of PIO
irq_set_enabled(PIO0_IRQ_1, true); // enable interrupt
// VGA HSYNC program
printf("Starting VGA hsync machine... ");
if (!pio_can_add_program(vga_hsync.pio, &vga_hsync_program))
panic("cannot add program");
vga_hsync.offset = pio_add_program(vga_hsync.pio, &vga_hsync_program);
vga_hsync.sm = pio_claim_unused_sm(vga_hsync.pio, true);
vga_hsync_program_init(vga_hsync.pio, vga_hsync.sm, vga_hsync.offset);
// low pulse is X pixels long, and SM runs at 4x of pixel clock
pio_sm_put_blocking(vga_hsync.pio, vga_hsync.sm, (64 - 2));
pio_sm_put_blocking(vga_hsync.pio, vga_hsync.sm, (640 + 16 - 1)); // 16 is front porch
printf("OK\n");
// VGA VSYNC program
printf("Starting VGA vsync machine... ");
if (!pio_can_add_program(vga_vsync.pio, &vga_vsync_program))
panic("cannot add program");
vga_vsync.offset = pio_add_program(vga_vsync.pio, &vga_vsync_program);
vga_vsync.sm = pio_claim_unused_sm(vga_vsync.pio, true);
vga_vsync_program_init(vga_vsync.pio, vga_vsync.sm, vga_vsync.offset);
// low pulse assert lasts for 3 horizontal lines, then adjust by one
pio_sm_put_blocking(vga_vsync.pio, vga_vsync.sm, 3 - 1);
pio_sm_put_blocking(vga_vsync.pio, vga_vsync.sm, 500 - 3 - 1);
printf("OK\n");
// VGA pixel program
vga_pixel_ptr = &vga_pixel;
printf("Starting VGA pixel machine... ");
if (!pio_can_add_program(vga_pixel.pio, &vga_pixel_program))
panic("cannot add program");
vga_pixel.offset = pio_add_program(vga_pixel.pio, &vga_pixel_program);
vga_pixel.sm = pio_claim_unused_sm(vga_pixel.pio, false);
vga_pixel_program_init(vga_pixel.pio, vga_pixel.sm, vga_pixel.offset);
pio_sm_put_blocking(vga_pixel.pio, vga_pixel.sm, 640 - 1);
printf("OK\n");
printf("Setting up DMA... ");
dma_channel = dma_claim_unused_channel(true);
dma_channel_config dma_config = dma_channel_get_default_config(dma_channel);
channel_config_set_transfer_data_size(&dma_config, DMA_SIZE_32);
channel_config_set_read_increment(&dma_config, true);
channel_config_set_write_increment(&dma_config, false);
channel_config_set_dreq(&dma_config, DREQ_PIO0_TX2);
dma_channel_set_irq0_enabled(dma_channel, true);
irq_set_exclusive_handler(DMA_IRQ_0, dma_handler);
irq_set_enabled(DMA_IRQ_0, true);
// -1 because first word is manually injected
// before the first DMA request, in order to
// avoid any possible delay
dma_channel_configure(dma_channel, &dma_config, &pio0_hw->txf[2], &frame[0],
HPIXEL * (VSPULSE + VPIXEL + VBBLANK) / 32 - 1, true);
dma_ready = true;
printf("OK\n");
printf("Now running.\n");
for (;;) for (;;)
{ {
@ -237,10 +60,14 @@ int main()
const uint16_t fc = frame_counter; const uint16_t fc = frame_counter;
const uint16_t x = fc % 640; const uint16_t x = fc % 640;
const uint16_t y = 380 + 100 * (abs(320 - x) / 640.0) * sin((fc % 640) / 12.738); const uint16_t y = 380 + 100 * (abs(320 - x) / 640.0) * sin((fc % 640) / 12.738);
if ((fc / 640) % 2)
set_pixel(x, y); set_pixel(x, y);
else
// 13 ms <=> 75 Hz
// Actually, there is a point in going in sync with vertical refresh,
// but let's just forget this for the demo.
sleep_ms(13);
clear_pixel(x, y); clear_pixel(x, y);
sleep_ms(5);
} }
} }

186
src/vga.c Normal file
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@ -0,0 +1,186 @@
#include "vga.h"
#include <stdio.h>
#include "hardware/dma.h"
#include "hardware/pio.h"
#include "hardware/structs/pio.h"
#include "framebuffer.h"
#include "vga.pio.h"
/**
* @brief Represents a program running on the SM of a PIO.
*
*/
typedef struct PIORun
{
PIO pio; //< executing PIO
uint offset; //< PIO memory offset for program
uint sm; //< executing SM
} PIORun;
static PIORun vga_hsync, vga_vsync, vga_pixel;
static PIORun *vga_pixel_ptr = &vga_pixel;
static bool dma_ready = false;
static int dma_channel;
unsigned long int frame_counter = 0;
static void vga_pixel_program_init(PIO pio, uint sm, uint offset)
{
// config function automatically declared by SDK scripts
// based on the names given to programs in .pio
pio_sm_config config = vga_pixel_program_get_default_config(offset);
// destination pins for OUT instructions
sm_config_set_out_pins(&config, 22, 1);
sm_config_set_out_shift(&config, true, true, 0);
pio_gpio_init(pio, 22);
pio_sm_set_consecutive_pindirs(pio, sm, 22, 1, true);
sm_config_set_wrap(&config, offset + vga_pixel_wrap_target, offset + vga_pixel_wrap);
pio_sm_init(pio, sm, offset, &config);
pio_sm_set_clkdiv_int_frac(pio, sm, 1, 0);
pio_sm_set_enabled(pio, sm, true);
}
static void vga_hsync_program_init(PIO pio, uint sm, uint offset)
{
pio_sm_config config = vga_hsync_program_get_default_config(offset);
// destination pins for SET instructions
sm_config_set_set_pins(&config, 20, 1);
pio_gpio_init(pio, 20);
pio_sm_set_consecutive_pindirs(pio, sm, 20, 1, true);
sm_config_set_wrap(&config, offset + vga_hsync_wrap_target, offset + vga_hsync_wrap);
pio_sm_init(pio, sm, offset, &config);
pio_sm_set_clkdiv_int_frac(pio, sm, 1, 0);
pio->sm->shiftctrl = (1 << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB);
pio_sm_set_enabled(pio, sm, true);
}
static void vga_vsync_program_init(PIO pio, uint sm, uint offset)
{
pio_sm_config config = vga_vsync_program_get_default_config(offset);
// destination pins for SET instructions
sm_config_set_set_pins(&config, 21, 1);
pio_gpio_init(pio, 21);
pio_sm_set_consecutive_pindirs(pio, sm, 21, 1, true);
sm_config_set_wrap(&config, offset + vga_vsync_wrap_target, offset + vga_vsync_wrap);
pio_sm_init(pio, sm, offset, &config);
pio_sm_set_clkdiv_int_frac(pio, sm, 1, 0);
pio->sm->shiftctrl = (1 << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB);
pio_sm_set_enabled(pio, sm, true);
}
void dma_handler(void)
{
// acknoweledge DMA
dma_hw->ints0 = 1 << dma_channel;
}
void new_frame_handler(void)
{
if (vga_pixel_ptr && dma_ready)
{
// Explicitly put the first uint32_t word in the FIFO,
// because, when PIO pulls data for the first time,
// and its FIFO is empty, the DMA controller takes "a while"
// to put the first word and keep up with the transfer,
// making the whole frame a bit offset to the right.
// Since front porch is very short, even the smallest delay,
// may disrupt the timing.
// Also note: despite the "blocking put", when this interrupt
// is serviced, PIO FIFO is always empty, so in practice
// this will never block.
pio_sm_put_blocking(vga_pixel_ptr->pio, vga_pixel_ptr->sm, 0);
// Start DMA (but skip the initial word, which has been put manually)
dma_channel_set_read_addr(dma_channel, &frame[4], true);
}
frame_counter++;
pio_interrupt_clear(pio0_hw, 1);
}
void vga_machines_init(void)
{
// Running programs on PIO
vga_hsync.pio = vga_vsync.pio = vga_pixel.pio = pio0;
// Prepare frame interrupt
// Frame interrupt is asserted on PIO0 interrupt 1 by SM1
pio_set_irq1_source_enabled(vga_vsync.pio, pis_interrupt1,
true); // allow SM1 of PIO to fire the interrupt
irq_set_exclusive_handler(PIO0_IRQ_1, new_frame_handler); // set handler for IRQ1 of PIO
irq_set_enabled(PIO0_IRQ_1, true); // enable interrupt
// VGA HSYNC program
printf("Starting VGA hsync machine... ");
if (!pio_can_add_program(vga_hsync.pio, &vga_hsync_program))
panic("cannot add program");
vga_hsync.offset = pio_add_program(vga_hsync.pio, &vga_hsync_program);
vga_hsync.sm = pio_claim_unused_sm(vga_hsync.pio, true);
vga_hsync_program_init(vga_hsync.pio, vga_hsync.sm, vga_hsync.offset);
// low pulse is X pixels long, and SM runs at 4x of pixel clock
pio_sm_put_blocking(vga_hsync.pio, vga_hsync.sm, (64 - 2));
pio_sm_put_blocking(vga_hsync.pio, vga_hsync.sm, (640 + 16 - 1)); // 16 is front porch
printf("OK\n");
// VGA VSYNC program
printf("Starting VGA vsync machine... ");
if (!pio_can_add_program(vga_vsync.pio, &vga_vsync_program))
panic("cannot add program");
vga_vsync.offset = pio_add_program(vga_vsync.pio, &vga_vsync_program);
vga_vsync.sm = pio_claim_unused_sm(vga_vsync.pio, true);
vga_vsync_program_init(vga_vsync.pio, vga_vsync.sm, vga_vsync.offset);
// low pulse assert lasts for 3 horizontal lines, then adjust by one
pio_sm_put_blocking(vga_vsync.pio, vga_vsync.sm, 3 - 1);
pio_sm_put_blocking(vga_vsync.pio, vga_vsync.sm, 500 - 3 - 1);
printf("OK\n");
// VGA pixel program
printf("Starting VGA pixel machine... ");
if (!pio_can_add_program(vga_pixel.pio, &vga_pixel_program))
panic("cannot add program");
vga_pixel.offset = pio_add_program(vga_pixel.pio, &vga_pixel_program);
vga_pixel.sm = pio_claim_unused_sm(vga_pixel.pio, false);
vga_pixel_program_init(vga_pixel.pio, vga_pixel.sm, vga_pixel.offset);
pio_sm_put_blocking(vga_pixel.pio, vga_pixel.sm, 640 - 1);
printf("OK\n");
printf("Setting up DMA... ");
dma_channel = dma_claim_unused_channel(true);
dma_channel_config dma_config = dma_channel_get_default_config(dma_channel);
channel_config_set_transfer_data_size(&dma_config, DMA_SIZE_32);
channel_config_set_read_increment(&dma_config, true);
channel_config_set_write_increment(&dma_config, false);
channel_config_set_dreq(&dma_config, DREQ_PIO0_TX2);
dma_channel_set_irq0_enabled(dma_channel, true);
irq_set_exclusive_handler(DMA_IRQ_0, dma_handler);
irq_set_enabled(DMA_IRQ_0, true);
// -1 because first word is manually injected
// before the first DMA request, in order to
// avoid any possible delay
dma_channel_configure(dma_channel, &dma_config, &pio0_hw->txf[2], &frame[0],
HPIXEL * (VSPULSE + VPIXEL + VBBLANK) / 32 - 1, true);
dma_ready = true;
printf("OK\n");
printf("Now running.\n");
}

8
src/vga.h Normal file
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@ -0,0 +1,8 @@
#ifndef VGA_H
#define VGA_H
void vga_machines_init(void);
extern unsigned long int frame_counter;
#endif // VGA_H