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src/vga.c
79
src/vga.c
@ -22,12 +22,26 @@ typedef struct PIORun
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uint sm; //< executing SM
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} PIORun;
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/*
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There are 3 SM running: horizontal and vertical sync, and pixels.
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See vga.pio for details.
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*/
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static PIORun vga_hsync, vga_vsync, vga_pixel;
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static bool dma_ready = false;
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static int dma_channel;
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static unsigned long int frame_counter = 0;
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static bool dma_ready = false; //< current DMA acceleration status
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static int dma_channel; //< DMA channel number, used to refill the vga_pixel FIFO
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static unsigned long int frame_counter = 0; //< current frame
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/**
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* @brief Setup system clocks.
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*
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* Main system clock must run at 126MHz,
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* which is 4 times pixel clock (31.5 MHz).
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* This allows SM to output one pixel every 4 clock cycles,
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* and to do some stuff in the mean time (eg. sending interrupts to sync with the other SM)
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*
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*/
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static void setup_clocks(void)
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{
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// disable resuscitation clock
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@ -52,9 +66,16 @@ static void setup_clocks(void)
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clock_configure(clk_peri, 0, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, 126 * MHZ, 126 * MHZ);
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}
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/**
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* @brief Initializes the VGA pixel shift machine.
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*
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* @param pio PIO peripheral to use.
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* @param sm SM to use.
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* @param offset PIO memory offset for program.
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*/
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static void vga_pixel_program_init(PIO pio, uint sm, uint offset)
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{
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// config function automatically declared by SDK scripts
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// config function is automatically declared by SDK scripts
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// based on the names given to programs in .pio
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pio_sm_config config = vga_pixel_program_get_default_config(offset);
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@ -72,6 +93,13 @@ static void vga_pixel_program_init(PIO pio, uint sm, uint offset)
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pio_sm_set_enabled(pio, sm, true);
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}
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/**
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* @brief Initializes the VGA horizontal sync machine.
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*
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* @param pio PIO peripheral to use.
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* @param sm SM to use.
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* @param offset PIO memory offset for program.
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*/
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static void vga_hsync_program_init(PIO pio, uint sm, uint offset)
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{
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pio_sm_config config = vga_hsync_program_get_default_config(offset);
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@ -90,6 +118,13 @@ static void vga_hsync_program_init(PIO pio, uint sm, uint offset)
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pio_sm_set_enabled(pio, sm, true);
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}
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/**
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* @brief Initializes the VGA vertical sync machine.
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*
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* @param pio PIO peripheral to use.
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* @param sm SM to use.
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* @param offset PIO memory offset for program.
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*/
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static void vga_vsync_program_init(PIO pio, uint sm, uint offset)
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{
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pio_sm_config config = vga_vsync_program_get_default_config(offset);
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@ -108,13 +143,20 @@ static void vga_vsync_program_init(PIO pio, uint sm, uint offset)
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pio_sm_set_enabled(pio, sm, true);
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}
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void dma_handler(void)
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/**
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* @brief DMA interrupt handler.
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*/
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static void dma_handler(void)
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{
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// acknoweledge DMA
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dma_hw->ints0 = 1 << dma_channel;
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}
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void new_frame_handler(void)
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/**
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* @brief Vertical sync interrupt handler.
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*
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*/
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static void new_frame_handler(void)
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{
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if (dma_ready)
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{
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@ -142,7 +184,6 @@ void new_frame_handler(void)
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void vga_machines_init(void)
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{
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// setup a proper system clock
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// (126MHz = 4 x 31.5 MHz pixel clock)
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setup_clocks();
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// Running programs on PIO
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@ -162,7 +203,10 @@ void vga_machines_init(void)
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vga_hsync.offset = pio_add_program(vga_hsync.pio, &vga_hsync_program);
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vga_hsync.sm = pio_claim_unused_sm(vga_hsync.pio, true);
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vga_hsync_program_init(vga_hsync.pio, vga_hsync.sm, vga_hsync.offset);
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// low pulse is X pixels long, and SM runs at 4x of pixel clock
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// push configuration words to horizontal sync machine FIFO
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// - hsync pulse duration (in pixel), assert time (low)
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// - hsync pulse duration (in pixel), idle time (high), minus back porch
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pio_sm_put_blocking(vga_hsync.pio, vga_hsync.sm, (64 - 2));
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pio_sm_put_blocking(vga_hsync.pio, vga_hsync.sm, (640 + 16 - 1)); // 16 is front porch
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printf("OK\n");
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@ -174,7 +218,9 @@ void vga_machines_init(void)
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vga_vsync.offset = pio_add_program(vga_vsync.pio, &vga_vsync_program);
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vga_vsync.sm = pio_claim_unused_sm(vga_vsync.pio, true);
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vga_vsync_program_init(vga_vsync.pio, vga_vsync.sm, vga_vsync.offset);
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// low pulse assert lasts for 3 horizontal lines, then adjust by one
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// push configuration words to vertical sync machine FIFO
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// - vsync pulse duration (in lines), assert time (low)
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// - vsync pulse duration (in lines), idle time (high)
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pio_sm_put_blocking(vga_vsync.pio, vga_vsync.sm, 3 - 1);
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pio_sm_put_blocking(vga_vsync.pio, vga_vsync.sm, 500 - 3 - 1);
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printf("OK\n");
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@ -186,6 +232,8 @@ void vga_machines_init(void)
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vga_pixel.offset = pio_add_program(vga_pixel.pio, &vga_pixel_program);
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vga_pixel.sm = pio_claim_unused_sm(vga_pixel.pio, false);
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vga_pixel_program_init(vga_pixel.pio, vga_pixel.sm, vga_pixel.offset);
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// push configuration word to pixel machine FIFO
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// - number of visible pixels in a line
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pio_sm_put_blocking(vga_pixel.pio, vga_pixel.sm, 640 - 1);
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printf("OK\n");
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@ -195,16 +243,18 @@ void vga_machines_init(void)
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channel_config_set_transfer_data_size(&dma_config, DMA_SIZE_32);
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channel_config_set_read_increment(&dma_config, true);
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channel_config_set_write_increment(&dma_config, false);
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// link Data Request signal of PIO SM2 TX FIFO to DMA
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channel_config_set_dreq(&dma_config, DREQ_PIO0_TX2);
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// setup transfer acknowledge interrupt
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dma_channel_set_irq0_enabled(dma_channel, true);
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irq_set_exclusive_handler(DMA_IRQ_0, dma_handler);
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irq_set_enabled(DMA_IRQ_0, true);
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// -1 because first word is manually injected
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// before the first DMA request, in order to
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// avoid any possible delay
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// pull one word less, because first word is manually injected
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// before the first DMA request, in order to avoid any possible delay
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// (see new frame interrupt handler)
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dma_channel_configure(dma_channel, &dma_config, &pio0_hw->txf[2], &frame[0],
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HPIXEL * (VSPULSE + VPIXEL + VBBLANK) / 32 - 1, true);
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@ -214,6 +264,11 @@ void vga_machines_init(void)
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printf("Now running.\n");
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}
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/**
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* @brief Get current frame counter.
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*
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* @return Current frame counter.
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*/
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unsigned long int vga_get_frame_counter(void)
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{
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return frame_counter;
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82
src/vga.pio
82
src/vga.pio
@ -1,60 +1,116 @@
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/*
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- horizontal sync pulse generation
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this machine commands the timing for the other machines too
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- vertical sync pulse generation
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counts the horizontal sync pulses and generated a vertical sync pulse accordingly
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- pixel machine
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horizontal sync machine also sends an interrupt when the back porch is finished,
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thus triggering the pixel machine to start shifting out the pixels
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*/
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/*
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Pixel Machine
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Wait for the "start-of-visible-line" interrupt signal,
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and output 640 pixels
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*/
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.program vga_pixel
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entrypoint_vga_pixel:
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// pull configuration into Y register
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// Y = number of visible pixels in the line
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pull
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mov y, osr
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.wrap_target
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mov x, y
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wait irq 7
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// loop lasts 4 SM clocks, which corresponds to 1 VGA pixel
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loop:
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out pins, 1 [2]
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jmp x-- loop
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.wrap
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/*
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Horizontal Sync Machine
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A line is composed by 840 pixels:
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- 64 sync pulse
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- 120 back porch
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- 640 visible area
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- 16 front porch
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*/
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.program vga_hsync
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entrypoint_vga_hsync:
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// pull configuration into ISR and OSR registers
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// ISR = sync pulse duration - 2 (64 pixel)
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// OSR = visible line + front porch - 1 (640 + 16 pixel)
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// Note: configuration contains desired value -1/-2,
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// because of how end-of-loop check is performed
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// and how time is spent in overhead instructions
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pull
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mov isr, osr
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pull
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// once configured, no more data is pulled from the TX FIFO,
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// so program wraps around here
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.wrap_target
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set pins, 0 [1]
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irq set 0
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mov x, isr
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set pins, 0 [1] // start pulse low
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irq set 0 // trigger "start-of-line" interrupt signal
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mov x, isr // load register X with sync pulse duration
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// +4 SM clocks elapsed (first VGA pixel)
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// loop for the duration of the low pulse (remaining 63 pixels)
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hsync_pulse:
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jmp x-- hsync_pulse [3]
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set pins, 1 [1]
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set y, 27
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set pins, 1 [1] // start pulse high (.5 pixel)
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// hardcoded backporch duration: 120 pixel => 120 x 4 = 480 SM clocks
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// but one pixel is already in the surronding logic, then only 476 clocks are cycled
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// where 476 = (27 + 1) * (16 + 1)
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set y, 27 // another .25 pixel
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hsync_back_porch:
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jmp y-- hsync_back_porch [16]
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irq set 7
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irq set 7 // trigger "start-of-visible-line" interrupt signal
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// (.25 more pixel)
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mov x, osr [3]
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mov x, osr [3] // load register X with remaining line duration (visible line + front porch)
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// also, just make this last 4 SM clocks (1 pixel)
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hsync_idle:
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jmp x-- hsync_idle [3]
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.wrap
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/*
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Vertical Sync Machine
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A frame is composed by 500 lines:
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- 3 vertical sync pulse
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- 16 back porch
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- 480 visible lines
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- 1 front porch
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*/
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.program vga_vsync
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entrypoint_vga_vsync:
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// Pull configuration into ISR and OSR registers
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// ISR = sync pulse assert duration - 1 (3 lines)
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// OSR = sync pulse idle duration - 1 (497 lines)
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pull
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mov isr, osr
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pull
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// once configured, no more data is pulled from the TX FIFO,
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// so program wraps around here
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.wrap_target
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mov x, isr
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mov x, isr // load register X with low pulse duration
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vsync_pulse:
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wait irq 0
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set pins, 0
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wait irq 0 // wait for "start-of-line" interrupt from hsync machine
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set pins, 0 // start pulse low
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jmp x-- vsync_pulse
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// trigger "start-of-frame" interrupt
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// (actually, 3 lines of the back porch are already passed)
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irq set 1
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mov x, osr
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mov x, osr // load register X with high pulse duration
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vsync_idle:
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wait irq 0
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set pins, 1
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