Richard Weickelt
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c98b0498a7
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Adding more functionality
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2018-08-31 11:04:38 +02:00 |
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Richard Weickelt
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64f440a15f
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Initial commit, doesn't compile
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2018-08-31 11:04:38 +02:00 |
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Richard Weickelt
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5a6578b99f
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Undo watchdog changes
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2018-08-31 11:04:38 +02:00 |
Edvard Pettersen
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2b0091246d
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UART0 arch driver impl
* Async read
* Renamed driver to uart0-arch
* Renamed arch/cpu source folder to dev/
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2018-08-31 11:04:38 +02:00 |
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Edvard Pettersen
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b30ef7d56d
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Added async read on UART
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2018-08-31 11:04:38 +02:00 |
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Richard Weickelt
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c99c3b4b5f
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Rewriting clock module based upon DPL
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2018-08-31 11:04:38 +02:00 |
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Edvard Pettersen
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c8023df8a5
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Added UART serial interface printing
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2018-08-31 11:04:38 +02:00 |
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Edvard Pettersen
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765e35ba7f
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Added working simplelink platform without netstack
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2018-08-31 11:04:38 +02:00 |
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Edvard Pettersen
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65ba0bb5a6
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Fixed remaking Makefiles, removed implicit %.o for %.elf, aligned
defines, added volatile qualifier for RAM vector pointer
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2018-08-31 11:04:37 +02:00 |
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Richard Weickelt
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f83579098b
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Resolve remarks
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2018-08-31 11:04:37 +02:00 |
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Richard Weickelt
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a40e5bc314
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Build the board file and add all libraries from the SDK
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2018-08-31 11:04:37 +02:00 |
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Edvard Pettersen
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12c9056cec
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Cleaned up CCFG configuration, and aligned CC13x0_cc26x0 and
CC13x2_CC26x2 CPU conf
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2018-08-31 11:04:37 +02:00 |
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Richard Weickelt
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c7aaefb4da
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Add board file deduction logic and board init stages
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2018-08-31 11:04:37 +02:00 |
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Edvard Pettersen
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b861190cb8
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Initial commit for rtimer-arch
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2018-08-31 11:04:37 +02:00 |
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Richard Weickelt
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be4131d277
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Add necessary SDK libraries and include paths
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2018-08-31 11:04:37 +02:00 |
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Edvard Pettersen
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ddd451a19b
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Compiling example of dummy simplelink platform
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2018-08-31 11:04:37 +02:00 |