cdfa8708e3
* f1xxx is baseline and always included * Cleaned up the names of uart and spi (no x in names) * Updated SPI configuration for WiSMote
296 lines
8.0 KiB
C
296 lines
8.0 KiB
C
/*
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* Copyright (c) 2006, Swedish Institute of Computer Science
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)$Id: uart1.c,v 1.24 2011/01/19 20:44:20 joxe Exp $
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*/
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/*
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* Machine dependent MSP430 UART1 code.
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*/
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#include "contiki.h"
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#include "sys/energest.h"
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#include "dev/uart1.h"
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#include "dev/watchdog.h"
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#include "sys/ctimer.h"
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#include "lib/ringbuf.h"
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static int (*uart1_input_handler)(unsigned char c);
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static volatile uint8_t rx_in_progress;
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static volatile uint8_t transmitting;
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#ifdef UART1_CONF_TX_WITH_INTERRUPT
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#define TX_WITH_INTERRUPT UART1_CONF_TX_WITH_INTERRUPT
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#else /* UART1_CONF_TX_WITH_INTERRUPT */
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#define TX_WITH_INTERRUPT 0
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#endif /* UART1_CONF_TX_WITH_INTERRUPT */
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#ifdef UART1_CONF_RX_WITH_DMA
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#define RX_WITH_DMA UART1_CONF_RX_WITH_DMA
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#else /* UART1_CONF_RX_WITH_DMA */
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#define RX_WITH_DMA 1
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#endif /* UART1_CONF_RX_WITH_DMA */
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#if TX_WITH_INTERRUPT
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#define TXBUFSIZE 128
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static struct ringbuf txbuf;
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static uint8_t txbuf_data[TXBUFSIZE];
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#endif /* TX_WITH_INTERRUPT */
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#if RX_WITH_DMA
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#define RXBUFSIZE 128
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static uint8_t rxbuf[RXBUFSIZE];
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static uint16_t last_size;
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static struct ctimer rxdma_timer;
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static void
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handle_rxdma_timer(void *ptr)
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{
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uint16_t size;
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size = DMA0SZ; /* Note: loop requires that size is less or eq to RXBUFSIZE */
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while(last_size != size) {
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/* printf("read: %c [%d,%d]\n", (unsigned char)rxbuf[RXBUFSIZE - last_size], */
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/* last_size, size); */
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uart1_input_handler((unsigned char)rxbuf[RXBUFSIZE - last_size]);
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last_size--;
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if(last_size == 0) last_size = RXBUFSIZE;
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}
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ctimer_reset(&rxdma_timer);
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}
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#endif /* RX_WITH_DMA */
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/*---------------------------------------------------------------------------*/
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uint8_t
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uart1_active(void)
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{
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return ((~ UTCTL1) & TXEPT) | rx_in_progress | transmitting;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart1_set_input(int (*input)(unsigned char c))
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{
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#if RX_WITH_DMA /* This needs to be called after ctimer process is started */
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ctimer_set(&rxdma_timer, CLOCK_SECOND/64, handle_rxdma_timer, NULL);
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#endif
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uart1_input_handler = input;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart1_writeb(unsigned char c)
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{
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watchdog_periodic();
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#if TX_WITH_INTERRUPT
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/* Put the outgoing byte on the transmission buffer. If the buffer
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is full, we just keep on trying to put the byte into the buffer
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until it is possible to put it there. */
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while(ringbuf_put(&txbuf, c) == 0);
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/* If there is no transmission going, we need to start it by putting
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the first byte into the UART. */
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if(transmitting == 0) {
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transmitting = 1;
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/* Loop until the transmission buffer is available. */
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/*while((IFG2 & UTXIFG1) == 0);*/
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TXBUF1 = ringbuf_get(&txbuf);
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}
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#else /* TX_WITH_INTERRUPT */
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/* Loop until the transmission buffer is available. */
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while((IFG2 & UTXIFG1) == 0);
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/* Transmit the data. */
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TXBUF1 = c;
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#endif /* TX_WITH_INTERRUPT */
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}
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/*---------------------------------------------------------------------------*/
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/**
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* Initalize the RS232 port.
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*
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*/
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void
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uart1_init(unsigned long ubr)
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{
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/* RS232 */
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P3DIR &= ~0x80; /* Select P37 for input (UART1RX) */
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P3DIR |= 0x40; /* Select P36 for output (UART1TX) */
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P3SEL |= 0xC0; /* Select P36,P37 for UART1{TX,RX} */
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UCTL1 = SWRST | CHAR; /* 8-bit character, UART mode */
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#if 0
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U1RCTL &= ~URXEIE; /* even erroneous characters trigger interrupts */
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#endif
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UTCTL1 = SSEL1; /* UCLK = MCLK */
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UBR01 = ubr;
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UBR11 = ubr >> 8;
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/*
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* UMCTL1 values calculated using
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* http://mspgcc.sourceforge.net/baudrate.html
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*/
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switch(ubr) {
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#if F_CPU == 3900000ul
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case UART1_BAUD2UBR(115200ul):
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UMCTL1 = 0xF7;
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break;
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case UART1_BAUD2UBR(57600ul):
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UMCTL1 = 0xED;
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break;
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case UART1_BAUD2UBR(38400ul):
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UMCTL1 = 0xD6;
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break;
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case UART1_BAUD2UBR(19200ul):
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UMCTL1 = 0x08;
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break;
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case UART1_BAUD2UBR(9600ul):
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UMCTL1 = 0x22;
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break;
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#elif F_CPU == 2457600ul
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case UART1_BAUD2UBR(115200ul):
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UMCTL1 = 0x4A;
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break;
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case UART1_BAUD2UBR(57600ul):
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UMCTL1 = 0x5B;
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break;
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default:
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/* 9600, 19200, 38400 don't require any correction */
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UMCTL1 = 0x00;
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#else
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#error Unsupported CPU speed in uart1.c
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#endif
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}
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ME2 &= ~USPIE1; /* USART1 SPI module disable */
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ME2 |= (UTXE1 | URXE1); /* Enable USART1 TXD/RXD */
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UCTL1 &= ~SWRST;
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/* XXX Clear pending interrupts before enable!!! */
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IFG2 &= ~URXIFG1;
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U1TCTL |= URXSE;
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rx_in_progress = 0;
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transmitting = 0;
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IE2 |= URXIE1; /* Enable USART1 RX interrupt */
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#if TX_WITH_INTERRUPT
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ringbuf_init(&txbuf, txbuf_data, sizeof(txbuf_data));
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IE2 |= UTXIE1; /* Enable USART1 TX interrupt */
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#endif /* TX_WITH_INTERRUPT */
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#if RX_WITH_DMA
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IE2 &= ~URXIE1; /* disable USART1 RX interrupt */
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/* UART1_RX trigger */
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DMACTL0 = DMA0TSEL_9;
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/* source address = RXBUF1 */
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DMA0SA = (unsigned int) &RXBUF1;
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DMA0DA = (unsigned int) &rxbuf;
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DMA0SZ = RXBUFSIZE;
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last_size = RXBUFSIZE;
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DMA0CTL = DMADT_4 + DMASBDB + DMADSTINCR_3 + DMAEN + DMAREQ;// DMAIE;
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msp430_add_lpm_req(MSP430_REQUIRE_LPM1);
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#endif /* RX_WITH_DMA */
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}
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/*---------------------------------------------------------------------------*/
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#if !RX_WITH_DMA
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#ifdef __IAR_SYSTEMS_ICC__
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#pragma vector=UART1RX_VECTOR
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__interrupt void
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#else
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interrupt(UART1RX_VECTOR)
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#endif
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uart1_rx_interrupt(void)
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{
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uint8_t c;
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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if(!(URXIFG1 & IFG2)) {
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/* Edge detect if IFG not set? */
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U1TCTL &= ~URXSE; /* Clear the URXS signal */
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U1TCTL |= URXSE; /* Re-enable URXS - needed here?*/
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rx_in_progress = 1;
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LPM4_EXIT;
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} else {
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rx_in_progress = 0;
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/* Check status register for receive errors. */
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if(URCTL1 & RXERR) {
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c = RXBUF1; /* Clear error flags by forcing a dummy read. */
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} else {
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c = RXBUF1;
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if(uart1_input_handler != NULL) {
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if(uart1_input_handler(c)) {
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LPM4_EXIT;
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}
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}
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}
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}
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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}
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#endif /* !RX_WITH_DMA */
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/*---------------------------------------------------------------------------*/
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#if TX_WITH_INTERRUPT
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#ifdef __IAR_SYSTEMS_ICC__
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#pragma vector=UART1TX_VECTOR
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__interrupt void
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#else
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interrupt(UART1TX_VECTOR)
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#endif
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uart1_tx_interrupt(void)
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{
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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if(ringbuf_elements(&txbuf) == 0) {
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transmitting = 0;
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} else {
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TXBUF1 = ringbuf_get(&txbuf);
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}
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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}
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#endif /* TX_WITH_INTERRUPT */
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/*---------------------------------------------------------------------------*/
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