semi working timer for skipping back porch
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48da25958e
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2abac03779
2
const.h
2
const.h
@ -1,4 +1,4 @@
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#pragma once
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#define VERTICAL_OFFSET 30
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#define HORIZONTAL_OFFSET_CYCLE 56
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#define HORIZONTAL_OFFSET 3
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61
main.S
61
main.S
@ -30,6 +30,19 @@ main:
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ldi r16, 0x3 ; external interrupt 0 and 1, mask enable
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sts EIMSK, r16
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ldi r16, 0x02 ; don't connect output pins to timer, CTC[1:0] mode
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sts TCCR0A, r16
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ldi r16, 0x03 ; CTC[2] mode, prescaler /64
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sts TCCR0B, r16
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; init variables
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ldi r16, 0
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sts frame, r16
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sts frame + 1, r16
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sts line + 1, r16
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ldi r16, 1
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sts line, r16
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sei ; global interrupt enable
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1:
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@ -56,14 +69,40 @@ int_horizontal_sync: ; +3
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enter:
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; here, +23 or +24 cycles have passed since horizontal sync
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; so, there are still ~168 cycles before first useful data
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; or 56 3-cycle instructions (HORIZONTAL_OFFSET_CYCLE)
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ldi r31, HORIZONTAL_OFFSET_CYCLE ; skip back porch
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1:
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dec r31
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brne 1b
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ldi r31, 0
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sts TCNT0, r31
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ldi r31, HORIZONTAL_OFFSET ; set counter TOP
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sts OCR0A, r31
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; do things
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ldi r31, 0x7 ; clear any pending interrupt
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sts TIFR0, r31
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lds r31, TIMSK0
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ori r31, 0x02 ; mask enable interrupt timer A
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sts TIMSK0, r31
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int_horizontal_sync_end:
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pop r30
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pop r31
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out IO(SREG), r31
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pop r31
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reti
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.global int_timer_0
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int_timer_0:
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; here we are at the beginning of the visible line
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push r31
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in r31, IO(SREG)
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push r31
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; turn off interrupt
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lds r31, TIMSK0
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andi r31, 0xfd ; mask disable interrupt timer A
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sts TIMSK0, r31
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; draw things
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lds r31, frame
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andi r31, 0x70
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cpi r31, 0
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breq 2f
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1:
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@ -73,14 +112,20 @@ enter:
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sbi IO(PORTB), 4
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nop
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cbi IO(PORTB), 4
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nop
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sbi IO(PORTB), 4
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nop
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cbi IO(PORTB), 4
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nop
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sbi IO(PORTB), 4
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nop
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cbi IO(PORTB), 4
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nop
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sbi IO(PORTB), 4
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nop
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cbi IO(PORTB), 4
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int_horizontal_sync_end:
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pop r30
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pop r31
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out IO(SREG), r31
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pop r31
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