Rewrite some non-real-time initialization code in C.
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51
main.S
51
main.S
@ -1,12 +1,14 @@
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; main.S
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;
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; This file is part of OSDY VideoCharGen
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; a do-it-yourself on-screen-display image generator
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; for superimposition of analog PAL signals
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;
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#include <avr/io.h>
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#include "macro.h"
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#include "const.h"
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.data
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image:
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.byte 0xff
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show_image:
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.byte 0x00
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@ -18,48 +20,19 @@ current_jump_table:
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.text
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.global main
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main:
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ldi r16, 0x30 ; port B, pin 4 and 5 as output, others as input
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sts DDRB, r16
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; set interrupt vectors at address 0x0, not bootloader
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; timing is important, see atmel datasheet
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ldi r16, (1 << IVCE)
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ldi r17, 0
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out IO(MCUCR), r16
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out IO(MCUCR), r17
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ldi r16, 0xa ; external interrupt 0 and 1, falling edge
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sts EICRA, r16
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ldi r16, 0x3 ; external interrupt 0 and 1, mask enable
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sts EIMSK, r16
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ldi r16, 0x02 ; don't connect output pins to timer, CTC[1:0] mode
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sts TCCR0A, r16
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ldi r16, 0x01 ; CTC[2] mode, no prescaler
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sts TCCR0B, r16
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.global main_asm
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main_asm:
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; init variables
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ldi r16, 0
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sts frame, r16
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sts frame + 1, r16
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sts line, r16
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ldi r16, 0xfe
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sts line + 1, r16
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ldi r16, 0xff
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sts image, r16
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ldi r16, 0
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sts show_image, r16
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; r0 always holds 0
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clr r0
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call setup_c
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sei ; global interrupt enable
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; global interrupt enable
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sei
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; endless loop
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1:
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rjmp 1b
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@ -182,7 +155,7 @@ check_if_released:
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in r31, IO(PINB)
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andi r31, 0x04
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; if transition mode == 1, then always show image
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; TODO an huge shitty spaghetti code
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; Nice to have: maybe this can be written better.
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breq 1f
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ldi r31, 0
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sts show_image, r31
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45
main.c
45
main.c
@ -1,21 +1,54 @@
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#include <avr/io.h>
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#include <avr/interrupt.h>
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/**
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* @file main.c
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* @author giomba@glgprograms.it
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* @brief OSDY main.
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*
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* @copyright Copyright RetrOfficina GLG Programs (c) 2022
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*
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* Video image generator superimposition for analog PAL signals,
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* with Atmega328, for your retro OSD titles.
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*
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*/
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#include "const.h"
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#include <avr/interrupt.h>
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#include <avr/io.h>
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#include <string.h>
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volatile uint16_t frame;
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volatile uint16_t line;
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volatile uint16_t frame = 0;
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volatile uint16_t line = 0xfe;
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volatile uint8_t image = 0xff;
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ISR(INT0_vect, ISR_NAKED) {
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// vertical sync interrupt
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asm("jmp int_vertical_sync");
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}
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ISR(INT1_vect, ISR_NAKED) {
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// horizontal sync interrupt
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asm("jmp int_horizontal_sync");
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}
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ISR(TIMER0_COMPA_vect, ISR_NAKED) {
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// back porch timer interrupt
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asm("jmp int_timer_0");
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}
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void setup_c() {
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}
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// external assembly main loop
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void main_asm(void);
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int main() {
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// port B, pin 4 and 5 as output, others as input
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DDRB |= 0x30;
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// set interrupt vectors at address 0x0, not bootloader
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// timing is important, see atmel datasheet
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_SFR_IO8(MCUCR) = (1 << IVCE);
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_SFR_IO8(MCUCR) = 0;
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EICRA = 0x0a; // external interrupt 0 and 1, falling edge
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EIMSK = 0x03; // external interrupt 0 and 1, mask enable
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TCCR0A = 0x02; // don't connect output pins to timer, CTC[1:0] mode
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TCCR0B = 0x01; // CTC[2] mode, no prescaler
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main_asm();
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}
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