videochargen/main.S

#include <avr/io.h>
#include "macro.h"
#include "const.h"

.data

frame:
.word 0

line:
.word 0

.text

.global main
main:
    ldi r16, 0x30       ; port B, pin 4 and 5 as output
    sts DDRB, r16

    ; set interrupt vectors at address 0x0, not bootloader
    ; timing is important, see atmel datasheet
    ldi r16, (1 << IVCE)
    ldi r17, 0
    out IO(MCUCR), r16
    out IO(MCUCR), r17

    ldi r16, 0xa        ; external interrupt 0 and 1, falling edge
    sts EICRA, r16

    ldi r16, 0x3        ; external interrupt 0 and 1, mask enable
    sts EIMSK, r16

    sei                 ; global interrupt enable

1:
    rjmp 1b

.global int_horizontal_sync
int_horizontal_sync:
    push r31
    in r31, IO(SREG)    ; status register
    push r31
    push r30

    ; if (line >= VERTICAL_OFFSET), then enter
    lds r30, line
    lds r31, line + 1
    adiw z, 1
    sts line, r30
    sts line + 1, r31
    cpi r31, 0
    brne enter
    cpi r30, VERTICAL_OFFSET
    brlo int_horizontal_sync_end

enter:
    ldi r31, HORIZONTAL_OFFSET_CYCLE    ; skip back porch
1:
    dec r31
    brne 1b

    ; do things
    lds r31, frame
    cpi r31, 0
    breq 2f
1:
    dec r31
    brne 1b
2:

    sbi IO(PORTB), 4
    nop
    nop
    nop
    nop
    nop
    cbi IO(PORTB), 4

int_horizontal_sync_end:
    pop r30
    pop r31
    out IO(SREG), r31
    pop r31
    reti

.global int_vertical_sync
int_vertical_sync:
    push r31
    in r31, IO(SREG)
    push r31
    push r30

    lds r31, frame + 1
    lds r30, frame
    adiw z, 1
    sts frame + 1, r31
    sts frame, r30

    ldi r30, 1
    ldi r31, 0
    sts line, r30
    sts line + 1, r31

int_vertical_sync_end:
    pop r30
    pop r31
    out IO(SREG), r31
    pop r31
    reti
first commit vertical line at about 1/3 of the horizontal line 2021-06-26 17:15:17 +00:00			`#include <avr/io.h>`
			`#include "macro.h"`
something strange is happening 2021-06-27 19:57:02 +00:00			`#include "const.h"`
first commit vertical line at about 1/3 of the horizontal line 2021-06-26 17:15:17 +00:00
			`.data`
"diagonal line" not vertically locked, just a test also not the whole screen, just a bit 2021-06-26 20:34:22 +00:00
something strange is happening 2021-06-27 19:57:02 +00:00			`frame:`
line, frame as words (16 bit) 2021-06-28 19:38:39 +00:00			`.word 0`
"diagonal line" not vertically locked, just a test also not the whole screen, just a bit 2021-06-26 20:34:22 +00:00
"diagonal line" not the whole screen, but vertically locked actually it has some issues, there is a single dot (at the end/beginning of a cycle) that messes up the horizontal sync and moves all the picture... must be fixed 2021-06-26 21:42:23 +00:00			`line:`
line, frame as words (16 bit) 2021-06-28 19:38:39 +00:00			`.word 0`
"diagonal line" not the whole screen, but vertically locked actually it has some issues, there is a single dot (at the end/beginning of a cycle) that messes up the horizontal sync and moves all the picture... must be fixed 2021-06-26 21:42:23 +00:00
first commit vertical line at about 1/3 of the horizontal line 2021-06-26 17:15:17 +00:00			`.text`

something strange is happening 2021-06-27 19:57:02 +00:00			`.global main`
			`main:`
			`ldi r16, 0x30 ; port B, pin 4 and 5 as output`
first commit vertical line at about 1/3 of the horizontal line 2021-06-26 17:15:17 +00:00			`sts DDRB, r16`

something strange is happening 2021-06-27 19:57:02 +00:00			`; set interrupt vectors at address 0x0, not bootloader`
			`; timing is important, see atmel datasheet`
			`ldi r16, (1 << IVCE)`
first commit vertical line at about 1/3 of the horizontal line 2021-06-26 17:15:17 +00:00			`ldi r17, 0`
			`out IO(MCUCR), r16`
			`out IO(MCUCR), r17`

"diagonal line" not the whole screen, but vertically locked actually it has some issues, there is a single dot (at the end/beginning of a cycle) that messes up the horizontal sync and moves all the picture... must be fixed 2021-06-26 21:42:23 +00:00			`ldi r16, 0xa ; external interrupt 0 and 1, falling edge`
first commit vertical line at about 1/3 of the horizontal line 2021-06-26 17:15:17 +00:00			`sts EICRA, r16`

"diagonal line" not the whole screen, but vertically locked actually it has some issues, there is a single dot (at the end/beginning of a cycle) that messes up the horizontal sync and moves all the picture... must be fixed 2021-06-26 21:42:23 +00:00			`ldi r16, 0x3 ; external interrupt 0 and 1, mask enable`
first commit vertical line at about 1/3 of the horizontal line 2021-06-26 17:15:17 +00:00			`sts EIMSK, r16`

something strange is happening 2021-06-27 19:57:02 +00:00			`sei ; global interrupt enable`
first commit vertical line at about 1/3 of the horizontal line 2021-06-26 17:15:17 +00:00
			`1:`
something strange is happening 2021-06-27 19:57:02 +00:00			`rjmp 1b`

"diagonal line" not the whole screen, but vertically locked actually it has some issues, there is a single dot (at the end/beginning of a cycle) that messes up the horizontal sync and moves all the picture... must be fixed 2021-06-26 21:42:23 +00:00			`.global int_horizontal_sync`
			`int_horizontal_sync:`
"diagonal line" not vertically locked, just a test also not the whole screen, just a bit 2021-06-26 20:34:22 +00:00			`push r31`
			`in r31, IO(SREG) ; status register`
			`push r31`
line, frame as words (16 bit) 2021-06-28 19:38:39 +00:00			`push r30`

			`; if (line >= VERTICAL_OFFSET), then enter`
			`lds r30, line`
			`lds r31, line + 1`
			`adiw z, 1`
			`sts line, r30`
			`sts line + 1, r31`
something strange is happening 2021-06-27 19:57:02 +00:00			`cpi r31, 0`
line, frame as words (16 bit) 2021-06-28 19:38:39 +00:00			`brne enter`
			`cpi r30, VERTICAL_OFFSET`
			`brlo int_horizontal_sync_end`
something strange is happening 2021-06-27 19:57:02 +00:00
vertical line, scrolling from left to right sufficiently handles the back/front porch without disrupting the sync signal todo improvement: compute a sensible amount of cycles to waste during the porch 2021-06-27 20:37:11 +00:00			`enter:`
			`ldi r31, HORIZONTAL_OFFSET_CYCLE ; skip back porch`
			`1:`
			`dec r31`
			`brne 1b`

			`; do things`
something strange is happening 2021-06-27 19:57:02 +00:00			`lds r31, frame`
vertical line, scrolling from left to right sufficiently handles the back/front porch without disrupting the sync signal todo improvement: compute a sensible amount of cycles to waste during the porch 2021-06-27 20:37:11 +00:00			`cpi r31, 0`
something strange is happening 2021-06-27 19:57:02 +00:00			`breq 2f`
			`1:`
"diagonal line" not vertically locked, just a test also not the whole screen, just a bit 2021-06-26 20:34:22 +00:00			`dec r31`
something strange is happening 2021-06-27 19:57:02 +00:00			`brne 1b`
vertical line, scrolling from left to right sufficiently handles the back/front porch without disrupting the sync signal todo improvement: compute a sensible amount of cycles to waste during the porch 2021-06-27 20:37:11 +00:00			`2:`

			`sbi IO(PORTB), 4`
			`nop`
			`nop`
			`nop`
			`nop`
			`nop`
			`cbi IO(PORTB), 4`
something strange is happening 2021-06-27 19:57:02 +00:00
"diagonal line" not the whole screen, but vertically locked actually it has some issues, there is a single dot (at the end/beginning of a cycle) that messes up the horizontal sync and moves all the picture... must be fixed 2021-06-26 21:42:23 +00:00			`int_horizontal_sync_end:`
line, frame as words (16 bit) 2021-06-28 19:38:39 +00:00			`pop r30`
"diagonal line" not vertically locked, just a test also not the whole screen, just a bit 2021-06-26 20:34:22 +00:00			`pop r31`
			`out IO(SREG), r31`
			`pop r31`
			`reti`
first commit vertical line at about 1/3 of the horizontal line 2021-06-26 17:15:17 +00:00
"diagonal line" not the whole screen, but vertically locked actually it has some issues, there is a single dot (at the end/beginning of a cycle) that messes up the horizontal sync and moves all the picture... must be fixed 2021-06-26 21:42:23 +00:00			`.global int_vertical_sync`
			`int_vertical_sync:`
			`push r31`
something strange is happening 2021-06-27 19:57:02 +00:00			`in r31, IO(SREG)`
			`push r31`
line, frame as words (16 bit) 2021-06-28 19:38:39 +00:00			`push r30`
something strange is happening 2021-06-27 19:57:02 +00:00
line, frame as words (16 bit) 2021-06-28 19:38:39 +00:00			`lds r31, frame + 1`
			`lds r30, frame`
			`adiw z, 1`
			`sts frame + 1, r31`
			`sts frame, r30`
something strange is happening 2021-06-27 19:57:02 +00:00
line, frame as words (16 bit) 2021-06-28 19:38:39 +00:00			`ldi r30, 1`
			`ldi r31, 0`
			`sts line, r30`
			`sts line + 1, r31`
something strange is happening 2021-06-27 19:57:02 +00:00
			`int_vertical_sync_end:`
line, frame as words (16 bit) 2021-06-28 19:38:39 +00:00			`pop r30`
something strange is happening 2021-06-27 19:57:02 +00:00			`pop r31`
			`out IO(SREG), r31`
"diagonal line" not the whole screen, but vertically locked actually it has some issues, there is a single dot (at the end/beginning of a cycle) that messes up the horizontal sync and moves all the picture... must be fixed 2021-06-26 21:42:23 +00:00			`pop r31`
			`reti`