giomba/videochargen
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videochargen/main.S

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ArmAsm
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#include <avr/io.h>
#include "macro.h"
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#include "const.h"
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.data
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frame:
line, frame as words (16 bit)
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.word 0
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line:
line, frame as words (16 bit)
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.word 0
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.text
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.global main
main:
ldi r16, 0x30 ; port B, pin 4 and 5 as output
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sts DDRB, r16
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; set interrupt vectors at address 0x0, not bootloader
; timing is important, see atmel datasheet
ldi r16, (1 << IVCE)
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ldi r17, 0
out IO(MCUCR), r16
out IO(MCUCR), r17
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ldi r16, 0xa ; external interrupt 0 and 1, falling edge
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sts EICRA, r16
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ldi r16, 0x3 ; external interrupt 0 and 1, mask enable
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sts EIMSK, r16
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ldi r16, 0x02 ; don't connect output pins to timer, CTC[1:0] mode
sts TCCR0A, r16
ldi r16, 0x03 ; CTC[2] mode, prescaler /64
sts TCCR0B, r16
; init variables
ldi r16, 0
sts frame, r16
sts frame + 1, r16
sts line + 1, r16
ldi r16, 1
sts line, r16
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sei ; global interrupt enable
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1:
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rjmp 1b
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.global int_horizontal_sync
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int_horizontal_sync: ; +3
push r31 ; +5
in r31, IO(SREG) ; +6, status register
push r31 ; +8
push r30 ; +10
line, frame as words (16 bit)
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; if (line >= VERTICAL_OFFSET), then enter
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lds r30, line ; +12
lds r31, line + 1 ; +14
adiw z, 1 ; +16
sts line, r30 ; +18
sts line + 1, r31 ; +20
cpi r31, 0 ; +21
brne enter ; +22, +23
cpi r30, VERTICAL_OFFSET ; +23
brlo int_horizontal_sync_end ; +24
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enter:
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; here, +23 or +24 cycles have passed since horizontal sync
; so, there are still ~168 cycles before first useful data
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ldi r31, 0
sts TCNT0, r31
ldi r31, HORIZONTAL_OFFSET ; set counter TOP
sts OCR0A, r31
ldi r31, 0x7 ; clear any pending interrupt
sts TIFR0, r31
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lds r31, TIMSK0
ori r31, 0x02 ; mask enable interrupt timer A
sts TIMSK0, r31
int_horizontal_sync_end:
pop r30
pop r31
out IO(SREG), r31
pop r31
reti
.global int_timer_0
int_timer_0:
; here we are at the beginning of the visible line
push r31
in r31, IO(SREG)
push r31
; turn off interrupt
lds r31, TIMSK0
andi r31, 0xfd ; mask disable interrupt timer A
sts TIMSK0, r31
; draw things
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lds r31, frame
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andi r31, 0x70
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cpi r31, 0
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breq 2f
1:
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dec r31
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brne 1b
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2:
sbi IO(PORTB), 4
nop
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cbi IO(PORTB), 4
nop
sbi IO(PORTB), 4
nop
cbi IO(PORTB), 4
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nop
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sbi IO(PORTB), 4
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nop
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cbi IO(PORTB), 4
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nop
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sbi IO(PORTB), 4
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nop
cbi IO(PORTB), 4
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pop r31
out IO(SREG), r31
pop r31
reti
first commit vertical line at about 1/3 of the horizontal line
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"diagonal line" not the whole screen, but vertically locked actually it has some issues, there is a single dot (at the end/beginning of a cycle) that messes up the horizontal sync and moves all the picture... must be fixed
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.global int_vertical_sync
int_vertical_sync:
push r31
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in r31, IO(SREG)
push r31
line, frame as words (16 bit)
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push r30
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line, frame as words (16 bit)
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lds r31, frame + 1
lds r30, frame
adiw z, 1
sts frame + 1, r31
sts frame, r30
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line, frame as words (16 bit)
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ldi r30, 1
ldi r31, 0
sts line, r30
sts line + 1, r31
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int_vertical_sync_end:
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pop r30
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pop r31
out IO(SREG), r31
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pop r31
reti
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