2021-06-26 17:15:17 +00:00
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#include <avr/io.h>
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#include "macro.h"
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2021-06-27 19:57:02 +00:00
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#include "const.h"
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2021-06-26 17:15:17 +00:00
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2021-08-12 16:26:03 +00:00
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.data
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image:
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.byte 0xff
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show_image:
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.byte 0x00
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button_next_image:
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.byte 0x0
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current_jump_table:
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.word 0x0
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2021-06-26 17:15:17 +00:00
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.text
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2021-06-27 19:57:02 +00:00
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.global main
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main:
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2021-08-12 16:26:03 +00:00
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ldi r16, 0x30 ; port B, pin 4 and 5 as output, others as input
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2021-06-26 17:15:17 +00:00
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sts DDRB, r16
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2021-06-27 19:57:02 +00:00
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; set interrupt vectors at address 0x0, not bootloader
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; timing is important, see atmel datasheet
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ldi r16, (1 << IVCE)
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2021-06-26 17:15:17 +00:00
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ldi r17, 0
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out IO(MCUCR), r16
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out IO(MCUCR), r17
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2021-06-26 21:42:23 +00:00
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ldi r16, 0xa ; external interrupt 0 and 1, falling edge
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2021-06-26 17:15:17 +00:00
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sts EICRA, r16
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2021-06-26 21:42:23 +00:00
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ldi r16, 0x3 ; external interrupt 0 and 1, mask enable
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2021-06-26 17:15:17 +00:00
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sts EIMSK, r16
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2021-07-03 09:54:31 +00:00
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ldi r16, 0x02 ; don't connect output pins to timer, CTC[1:0] mode
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sts TCCR0A, r16
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2021-07-03 10:05:49 +00:00
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ldi r16, 0x01 ; CTC[2] mode, no prescaler
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2021-07-03 09:54:31 +00:00
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sts TCCR0B, r16
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; init variables
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ldi r16, 0
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sts frame, r16
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sts frame + 1, r16
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sts line, r16
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2021-08-11 20:26:35 +00:00
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ldi r16, 0xfe
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sts line + 1, r16
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2021-08-12 16:26:03 +00:00
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ldi r16, 0xff
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sts image, r16
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ldi r16, 0
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sts show_image, r16
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2021-07-03 09:54:31 +00:00
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2021-08-10 07:26:51 +00:00
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; r0 always holds 0
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clr r0
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2021-07-03 13:44:01 +00:00
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call setup_c
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2021-07-03 13:02:01 +00:00
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2021-06-27 19:57:02 +00:00
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sei ; global interrupt enable
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2021-06-26 17:15:17 +00:00
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1:
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2021-06-27 19:57:02 +00:00
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rjmp 1b
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2021-06-26 21:42:23 +00:00
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.global int_horizontal_sync
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2021-06-28 19:54:25 +00:00
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int_horizontal_sync: ; +3
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push r31 ; +5
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in r31, IO(SREG) ; +6, status register
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push r31 ; +8
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push r30 ; +10
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2021-06-28 19:38:39 +00:00
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; if (line >= VERTICAL_OFFSET), then enter
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2021-06-28 19:54:25 +00:00
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lds r30, line ; +12
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lds r31, line + 1 ; +14
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adiw z, 1 ; +16
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sts line, r30 ; +18
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sts line + 1, r31 ; +20
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cpi r31, 0 ; +21
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2021-08-10 07:26:51 +00:00
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breq enter ; +23
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jmp int_horizontal_sync_end
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2021-06-27 19:57:02 +00:00
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2021-06-27 20:37:11 +00:00
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enter:
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2021-06-28 19:54:25 +00:00
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; here, +23 or +24 cycles have passed since horizontal sync
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; so, there are still ~168 cycles before first useful data
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2021-07-03 09:54:31 +00:00
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ldi r31, 0
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sts TCNT0, r31
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ldi r31, HORIZONTAL_OFFSET ; set counter TOP
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sts OCR0A, r31
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ldi r31, 0x7 ; clear any pending interrupt
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sts TIFR0, r31
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2021-06-27 20:37:11 +00:00
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2021-07-03 09:54:31 +00:00
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lds r31, TIMSK0
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ori r31, 0x02 ; mask enable interrupt timer A
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sts TIMSK0, r31
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int_horizontal_sync_end:
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pop r30
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pop r31
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out IO(SREG), r31
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pop r31
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reti
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.global int_timer_0
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int_timer_0:
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; here we are at the beginning of the visible line
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push r31
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in r31, IO(SREG)
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push r31
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2021-07-03 13:02:01 +00:00
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push r30
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push r29
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2021-07-03 09:54:31 +00:00
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; turn off interrupt
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lds r31, TIMSK0
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andi r31, 0xfd ; mask disable interrupt timer A
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sts TIMSK0, r31
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2021-08-12 16:26:03 +00:00
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lds r31, show_image
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cpi r31, 0x1
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brne jump_table_return_address
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lds zl, current_jump_table
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lds zh, current_jump_table + 1
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; ldi zl, pm_lo8(line_jump_table_0)
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; ldi zh, pm_hi8(line_jump_table_0)
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2021-08-12 16:26:03 +00:00
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clr r0
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2021-08-10 07:26:51 +00:00
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lds r29, line
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add zl, r29
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adc zh, r0
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add zl, r29
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adc zh, r0
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ijmp
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2021-06-27 19:57:02 +00:00
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2021-08-11 07:04:59 +00:00
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.global jump_table_return_address
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jump_table_return_address:
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2021-07-03 13:02:01 +00:00
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pop r29
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pop r30
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2021-06-26 20:34:22 +00:00
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pop r31
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out IO(SREG), r31
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pop r31
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reti
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2021-06-26 17:15:17 +00:00
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2021-06-26 21:42:23 +00:00
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.global int_vertical_sync
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int_vertical_sync:
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push r31
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2021-06-27 19:57:02 +00:00
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in r31, IO(SREG)
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push zl
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push zh
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push yl
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push yh
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2021-06-27 19:57:02 +00:00
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2021-06-28 19:38:39 +00:00
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lds r31, frame + 1
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lds r30, frame
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adiw z, 1
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sts frame + 1, r31
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sts frame, r30
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2021-06-27 19:57:02 +00:00
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2021-06-28 19:38:39 +00:00
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ldi r30, 1
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ldi r31, 0
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sts line, r30
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sts line + 1, r31
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2021-06-27 19:57:02 +00:00
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2021-08-12 16:26:03 +00:00
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; check button
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in r31, IO(PINB)
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andi r31, 0x08
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breq check_if_released
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ldi r31, 1
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sts button_next_image, r31
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jmp int_vertical_sync_end
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check_if_released:
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lds r31, button_next_image
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cpi r31, 1
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brne int_vertical_sync_end
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; here button is released
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2021-08-12 20:53:27 +00:00
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; read transition mode
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in r31, IO(PINB)
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andi r31, 0x04
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; if transition mode == 1, then always show image
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; TODO an huge shitty spaghetti code
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breq 1f
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ldi r31, 0
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sts show_image, r31
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1:
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2021-08-12 16:26:03 +00:00
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lds r31, show_image
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cpi r31, 1
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breq 1f
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ldi r31, 1
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sts show_image, r31
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rjmp 2f
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1:
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ldi r31, 0
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sts show_image, r31
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rjmp end_button_release
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2:
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; show image
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ldi zl, pm_lo8(line_jump_table_0)
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ldi zh, pm_hi8(line_jump_table_0)
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clr yl
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lds yh, image
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inc yh
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sts image, yh
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add zh, yh
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add zh, yh
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sts current_jump_table, zl
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sts current_jump_table + 1, zh
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ldi r31, 0x01
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sts show_image, r31
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end_button_release:
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clr yl
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sts button_next_image, yl
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2021-06-27 19:57:02 +00:00
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int_vertical_sync_end:
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2021-08-12 16:26:03 +00:00
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pop yh
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pop yl
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pop zh
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pop zl
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2021-06-27 19:57:02 +00:00
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out IO(SREG), r31
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2021-06-26 21:42:23 +00:00
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pop r31
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reti
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