|
|
1272be8914
|
Clean setup of PLL at 126MHz (4x 31.5MHz = VGA pixel clock)
|
2022-10-15 23:07:03 +02:00 |
|
|
|
97dbd73f39
|
Add README.md.
|
2022-10-15 22:55:18 +02:00 |
|
|
|
9a931a44ad
|
More fine-tuning for the frequency.
|
2022-10-15 22:51:25 +02:00 |
|
|
|
1281f0bea6
|
Use user-provided SDK.
|
2022-10-15 22:51:12 +02:00 |
|
|
|
8b67fe9eda
|
pio_sm_put_blocking() unable to keep FIFO topped.
|
2022-10-15 18:42:46 +02:00 |
|
|
|
9b596c80aa
|
Pixels in sync with VSYNC and HSYNC.
|
2022-10-15 15:08:22 +02:00 |
|
|
|
6b6b76b212
|
Fix autopull on PIO0 using SDK setup functions.
|
2022-10-13 22:05:49 +02:00 |
|
|
|
151afb08b0
|
Stable VGA 640x460@75Hz. Black screen.
|
2022-10-12 22:09:16 +02:00 |
|
|
|
d805003349
|
Put hsync and vsync in phase.
|
2022-10-12 20:54:29 +02:00 |
|
|
|
a5339f6fcf
|
Add vertical sync to VGA (out of phase).
|
2022-10-12 20:44:26 +02:00 |
|
|
|
ed29e27f80
|
Add "documentation".
|
2022-10-12 20:31:54 +02:00 |
|
|
|
074ba919d7
|
Rename vga_sync to vga_hsync, because that's all that it does.
|
2022-10-12 20:30:29 +02:00 |
|
|
|
0f31cfb22d
|
Free-running VGA horizontal sync.
|
2022-10-12 20:29:11 +02:00 |
|
|
|
55559b6b89
|
Horizontal sync experiment.
|
2022-10-11 20:39:22 +02:00 |
|
|
|
c17a9b1018
|
Add two running state machines.
|
2022-10-10 21:48:16 +02:00 |
|
|
|
73195267cb
|
IntelliSense and formatting options.
|
2022-10-10 19:11:45 +02:00 |
|
|
|
bbe42f31bb
|
Add freerunning VGA pixel clock draft.
|
2022-10-10 19:10:52 +02:00 |
|
|
|
a81931cac6
|
Add SDK and examples modules.
|
2022-10-10 19:10:30 +02:00 |
|
|
|
2c815afd2b
|
First commit. Sample standalone project and build setup.
|
2022-10-09 17:11:05 +02:00 |
|
