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0cf72757e9
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More adjustments.
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2022-10-17 18:15:52 +02:00 |
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0b751fd1c0
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More stabilization.
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2022-10-17 16:52:15 +02:00 |
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fc3ed64e9e
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Improve code readability.
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2022-10-16 20:44:19 +02:00 |
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7a79fdd6d8
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More stuff.
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2022-10-16 20:18:00 +02:00 |
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1d68748f50
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A cross. Sort of. Also, remember that program is 32 words per PIO, not SM.
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2022-10-16 20:00:26 +02:00 |
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d40f208ce0
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Vertical dashed line with DMA. WIP.
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2022-10-16 00:09:51 +02:00 |
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1272be8914
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Clean setup of PLL at 126MHz (4x 31.5MHz = VGA pixel clock)
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2022-10-15 23:07:03 +02:00 |
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97dbd73f39
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Add README.md.
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2022-10-15 22:55:18 +02:00 |
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9a931a44ad
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More fine-tuning for the frequency.
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2022-10-15 22:51:25 +02:00 |
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1281f0bea6
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Use user-provided SDK.
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2022-10-15 22:51:12 +02:00 |
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8b67fe9eda
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pio_sm_put_blocking() unable to keep FIFO topped.
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2022-10-15 18:42:46 +02:00 |
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9b596c80aa
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Pixels in sync with VSYNC and HSYNC.
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2022-10-15 15:08:22 +02:00 |
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6b6b76b212
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Fix autopull on PIO0 using SDK setup functions.
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2022-10-13 22:05:49 +02:00 |
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151afb08b0
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Stable VGA 640x460@75Hz. Black screen.
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2022-10-12 22:09:16 +02:00 |
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d805003349
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Put hsync and vsync in phase.
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2022-10-12 20:54:29 +02:00 |
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a5339f6fcf
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Add vertical sync to VGA (out of phase).
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2022-10-12 20:44:26 +02:00 |
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ed29e27f80
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Add "documentation".
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2022-10-12 20:31:54 +02:00 |
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074ba919d7
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Rename vga_sync to vga_hsync, because that's all that it does.
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2022-10-12 20:30:29 +02:00 |
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0f31cfb22d
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Free-running VGA horizontal sync.
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2022-10-12 20:29:11 +02:00 |
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55559b6b89
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Horizontal sync experiment.
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2022-10-11 20:39:22 +02:00 |
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c17a9b1018
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Add two running state machines.
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2022-10-10 21:48:16 +02:00 |
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73195267cb
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IntelliSense and formatting options.
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2022-10-10 19:11:45 +02:00 |
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bbe42f31bb
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Add freerunning VGA pixel clock draft.
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2022-10-10 19:10:52 +02:00 |
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a81931cac6
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Add SDK and examples modules.
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2022-10-10 19:10:30 +02:00 |
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2c815afd2b
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First commit. Sample standalone project and build setup.
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2022-10-09 17:11:05 +02:00 |
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